Min Gyu Kim, V. Kratyuk, P. Hanumolu, G. Ahn, Sunwoo Kwon, U. Moon
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引用次数: 3
摘要
提出了一种10位50ms /s的流水线ADC。在MDAC操作中使用了一个25db开环直流增益放大器。由于使用参考缩放方案与背景偏移校准相结合，因此可以容忍极端的低opamp直流增益。在管道中插入一个中间增益级，以补偿基准和信号摆幅的累积减小。采用90 nm CMOS工艺实现的原型IC实现了-63.2 dB THD, 48.8 dB SNR和48.6 dB SNDR，同时从1 V电源消耗8 mW。
In 10-bit 50 MS/s pipelined ADC is presented. A 25 dB open loop dc gain amplifier is employed in the MDAC operation. The low opamp dc gain in the extreme is tolerated due to the use of a reference scaling scheme in conjunction with a background offset calibration. An intermediate gain stage is inserted into the pipeline to compensate for the accumulated reduction of reference and signal swing. The prototype IC implemented in a 90 nm CMOS process achieves -63.2 dB THD, 48.8 dB SNR, and 48.6 dB SNDR, while consuming 8 mW from a 1 V supply.
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