{"title":"SpiNNaker和并行芯片多处理器的神经形态采样","authors":"Daniel R. Mendat, S. Chin, S. Furber, A. Andreou","doi":"10.1109/LASCAS.2016.7451094","DOIUrl":null,"url":null,"abstract":"We present a bio-inspired, hardware/software architecture to perform Markov Chain Monte Carlo sampling on probabilistic graphical models using energy aware hardware. We have developed algorithms and programming data flows for two recently developed multiprocessor architectures, the SpiNNaker and Parallella. We employ a neurally inspired sampling algorithm that abstracts the functionality of neurons in a biological network and exploits the neural dynamics to implement the sampling process. This algorithm maps nicely on the two hardware systems. Speedups as high as 1000 fold are achieved when performing inference using this approach, compared to algorithms running on traditional engineering workstations.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Neuromorphic sampling on the SpiNNaker and parallella chip multiprocessors\",\"authors\":\"Daniel R. Mendat, S. Chin, S. Furber, A. Andreou\",\"doi\":\"10.1109/LASCAS.2016.7451094\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a bio-inspired, hardware/software architecture to perform Markov Chain Monte Carlo sampling on probabilistic graphical models using energy aware hardware. We have developed algorithms and programming data flows for two recently developed multiprocessor architectures, the SpiNNaker and Parallella. We employ a neurally inspired sampling algorithm that abstracts the functionality of neurons in a biological network and exploits the neural dynamics to implement the sampling process. This algorithm maps nicely on the two hardware systems. Speedups as high as 1000 fold are achieved when performing inference using this approach, compared to algorithms running on traditional engineering workstations.\",\"PeriodicalId\":129875,\"journal\":{\"name\":\"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)\",\"volume\":\"55 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LASCAS.2016.7451094\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LASCAS.2016.7451094","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Neuromorphic sampling on the SpiNNaker and parallella chip multiprocessors
We present a bio-inspired, hardware/software architecture to perform Markov Chain Monte Carlo sampling on probabilistic graphical models using energy aware hardware. We have developed algorithms and programming data flows for two recently developed multiprocessor architectures, the SpiNNaker and Parallella. We employ a neurally inspired sampling algorithm that abstracts the functionality of neurons in a biological network and exploits the neural dynamics to implement the sampling process. This algorithm maps nicely on the two hardware systems. Speedups as high as 1000 fold are achieved when performing inference using this approach, compared to algorithms running on traditional engineering workstations.