{"title":"基于DSP算法的实现提高了残数系统的面积效率","authors":"M. Mahesh, Satrajit Gupta, M. Mehendale","doi":"10.1109/ICVD.1999.745179","DOIUrl":null,"url":null,"abstract":"Residue Number System based applications involve modulo-arithmetic which is typically implemented using look-up-tables (LUTs) for a small value of modulus. In this paper we present a data coding technique to minimize the area of these LUTs when implemented using two level logic structures such as PLAs. We also present a technique that exploits the symmetry in these computations to further optimize the LUTs. Results show that area improvement of upto 66% can be achieved using these techniques.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Improving area efficiency of residue number system based implementation of DSP algorithms\",\"authors\":\"M. Mahesh, Satrajit Gupta, M. Mehendale\",\"doi\":\"10.1109/ICVD.1999.745179\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Residue Number System based applications involve modulo-arithmetic which is typically implemented using look-up-tables (LUTs) for a small value of modulus. In this paper we present a data coding technique to minimize the area of these LUTs when implemented using two level logic structures such as PLAs. We also present a technique that exploits the symmetry in these computations to further optimize the LUTs. Results show that area improvement of upto 66% can be achieved using these techniques.\",\"PeriodicalId\":443373,\"journal\":{\"name\":\"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-01-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVD.1999.745179\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1999.745179","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Improving area efficiency of residue number system based implementation of DSP algorithms
Residue Number System based applications involve modulo-arithmetic which is typically implemented using look-up-tables (LUTs) for a small value of modulus. In this paper we present a data coding technique to minimize the area of these LUTs when implemented using two level logic structures such as PLAs. We also present a technique that exploits the symmetry in these computations to further optimize the LUTs. Results show that area improvement of upto 66% can be achieved using these techniques.
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