抗单事件干扰(SEU)的12T抗辐射存储单元设计

Chunyan Hu, S. Yue, Shijin Lu
{"title":"抗单事件干扰(SEU)的12T抗辐射存储单元设计","authors":"Chunyan Hu, S. Yue, Shijin Lu","doi":"10.1109/ICAM.2017.8242164","DOIUrl":null,"url":null,"abstract":"A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in circuit design compared to the DICE cell, which reduces the sensitivity to single event multiple-node upsets (SE-MNU). Hspice simulation shows that it has an excellent performance considering read and write access time with an acceptable SNM. Circuit-SEU simulation demonstrates that it is not only immune to upsets any single sensitive node, but also tolerant to multiple node upset on specific nodes with sharing charge of 100fC.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Design of a novel 12T radiation hardened memory cell tolerant to single event upsets (SEU)\",\"authors\":\"Chunyan Hu, S. Yue, Shijin Lu\",\"doi\":\"10.1109/ICAM.2017.8242164\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in circuit design compared to the DICE cell, which reduces the sensitivity to single event multiple-node upsets (SE-MNU). Hspice simulation shows that it has an excellent performance considering read and write access time with an acceptable SNM. Circuit-SEU simulation demonstrates that it is not only immune to upsets any single sensitive node, but also tolerant to multiple node upset on specific nodes with sharing charge of 100fC.\",\"PeriodicalId\":117801,\"journal\":{\"name\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAM.2017.8242164\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAM.2017.8242164","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16

摘要

针对65纳米CMOS技术中的单事件干扰(SEU)问题,提出了一种新型的抗辐射12T存储单元(RH-12T)。它通过用NMOS包围输出节点,消除了敏感的“0”存储节点扰动的可能性,实现了对任何单个节点扰动的全电阻。此外,与DICE单元相比,电路设计中获得的节点对灵敏度较低,从而降低了对单事件多节点异常(SE-MNU)的灵敏度。Hspice仿真表明,在考虑读写访问时间的情况下,该方法具有良好的性能,SNM可接受。电路- seu仿真结果表明,该算法不仅不受单个敏感节点的干扰,而且可以在共享电荷为100fC的特定节点上容忍多个节点的干扰。
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Design of a novel 12T radiation hardened memory cell tolerant to single event upsets (SEU)
A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in circuit design compared to the DICE cell, which reduces the sensitivity to single event multiple-node upsets (SE-MNU). Hspice simulation shows that it has an excellent performance considering read and write access time with an acceptable SNM. Circuit-SEU simulation demonstrates that it is not only immune to upsets any single sensitive node, but also tolerant to multiple node upset on specific nodes with sharing charge of 100fC.
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