10nm SOI器件源-漏隧穿的实验表征

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI:10.1109/SOI.2005.1563525

J. Lolivier, X. Jehl, Q. Rafhay, T. Poiroux, M. Vinet, B. Previtali, M. Sanquer, F. Balestra, S. Deleonibus

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引用次数: 5

摘要

这项工作涉及低至4K的完全耗尽SOI MOSFET的电气特性，物理栅极长度低至10nm。温度测量用于突出源漏隧道:这是第一次在室温下得到证明。最后观察到共振隧穿效应。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Experimental characterization of source-to-drain tunneling in 10nm SOI devices

This work deals with the electrical characterization down to 4K of fully depleted SOI MOSFET with a physical gate length down to 10nm. Temperature measurements are used to highlight source to drain tunneling: which is evidenced at room temperature for the first time. Finally resonant tunneling effect is observed.

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2005 IEEE International SOI Conference Proceedings

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