基于0.18μm SOI的相位相干7位数字阶跃衰减器

Arash Ebrahimi Jarihani, F. Koçer
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引用次数: 6

摘要

提出了一种新型的数字阶跃衰减器(DSA),在衰减状态和频率变化下具有低相位变化。这是在保持所有其他规格与最先进的水平相当的同时实现的。为了补偿相移,使用了许多可切换的相位补偿块。与之前的研究不同,这项工作在商用4×4四平无引线(QFN)封装中实现了非常低的相位变化,其中线键效应非常显著。所提出的衰减器具有7位控制,衰减范围为0至31.75 dB,步长为0.25 dB,并在宽频率范围内实现准确的衰减设置。该衰减器采用商用0.18 pm射频绝缘体上硅(SOI)工艺制造。测量结果表明,衰减器的幅值误差小于1 dB,而在2.2 GHz范围内引入的最大相移为±3°,在2.2 - 3.5 GHz范围内引入的最大相移小于±6°。与商用衰减器相比,这种方法提供了至少2.5倍的相移改进。输入1db压缩点和IIP3的测量值通常分别高于35dbm和45dbm。包括衬垫在内的总芯片尺寸为1.95mm × 0.95mm。
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A phase coherent 7-bit digital step attenuator on 0.18μm SOI
We present a novel digital step attenuator (DSA) with low phase variation under attenuation state and frequency changes. This is achieved while keeping all other specifications comparable with the state-of-the-art. To compensate the phase shift, a number of switchable phase compensating blocks are employed. Unlike previous studies, this work achieves very low phase variation in a commercial, 4×4 quad-flat no-leads (QFN) package, where wirebond effects are significant. The proposed attenuator has 7-bit control with 0 to 31.75 dB attenuation range with 0.25 dB step sizes and achieves accurate attenuation settings in a wide frequency range. The attenuator is fabricated in a commercial 0.18 pm RF silicon-on-insulator (SOI) process. The measurement results show that the attenuator has an amplitude error of less than 1 dB, while introducing a maximum of ±3° phase shift up to 2.2 GHz and less than ±6° between 2.2–3.5 GHz. This approach provides at least 2.5-fold improvement in the phase shift when compared to commercial attenuators. The input 1 dB compression point and IIP3 are measured typically higher than 35 dBm and 45 dBm, respectively. Total chip size, including pads, is 1.95mm × 0.95mm.
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