{"title":"下一代环境，用于极快的测试模式生成","authors":"Gabriele Pulini, S. Hamacher","doi":"10.1109/EURDAC.1993.410671","DOIUrl":null,"url":null,"abstract":"The importance of test in ASIC and IC design is discussed, and some new design-for-test (DFT) strategies are presented. The advantages of a specific method for test vector creation and validation that tightly links two scan-test tools into the target design flow are described. These tools are a sequential, partial-scan automatic test pattern generator (ATPG) and an ATPG optimized for full-scan designs. Some customer results with these tools are presented as well.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Next generation environment for extremely fast test pattern generation\",\"authors\":\"Gabriele Pulini, S. Hamacher\",\"doi\":\"10.1109/EURDAC.1993.410671\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The importance of test in ASIC and IC design is discussed, and some new design-for-test (DFT) strategies are presented. The advantages of a specific method for test vector creation and validation that tightly links two scan-test tools into the target design flow are described. These tools are a sequential, partial-scan automatic test pattern generator (ATPG) and an ATPG optimized for full-scan designs. Some customer results with these tools are presented as well.<<ETX>>\",\"PeriodicalId\":339176,\"journal\":{\"name\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"volume\":\"1 3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-09-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1993.410671\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410671","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Next generation environment for extremely fast test pattern generation
The importance of test in ASIC and IC design is discussed, and some new design-for-test (DFT) strategies are presented. The advantages of a specific method for test vector creation and validation that tightly links two scan-test tools into the target design flow are described. These tools are a sequential, partial-scan automatic test pattern generator (ATPG) and an ATPG optimized for full-scan designs. Some customer results with these tools are presented as well.<>
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