开关电流电路的可测试性设计

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI:10.1109/VTEST.1998.670892

F. Azaïs, M. Renovell, Y. Bertrand, J.-C. Bodin

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引用次数: 6

摘要

本文提出了一种DFT技术，该技术提供了开关电流电路中每个存储单元的完全可控性和可观察性。该技术被证明适用于任何类型的SI电路，非常容易实现自动化，对电路性能没有任何影响。实际上，保留了电路的硬件配置，并且仅管理了时序配置以将电路转换为测试模式下的完全可测试结构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design-for-testability for switched-current circuits

In this paper a DFT technique is proposed that provides the full controllability and observability of each memory cell of a switched-current circuit. The technique is proven to be applicable to any kind of SI circuits, very easy to automate and without any impact on the circuit performance. Indeed, the hardware configuration of the circuit is preserved and only the timing configuration is managed to convert the circuit into a fully testable structure in test mode.

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Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

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