用于逻辑兼容高密度dram的新型合并增益单元

1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI:10.1109/VLSIT.1997.623745

Mukai, Hayashi, Komatsu

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引用次数: 1

摘要

提出了一种逻辑兼容合并DRAM增益单元的结构单元，该单元的尺寸几乎可以缩小到一个晶体管面积，并且工艺步骤的增加很小。由于两个p+栅极区域之间的n沟道区域的JFET效应，它可以大大改善“1”和“0”状态的分离。这种新电池不需要新材料，也不需要新设备。非破坏性读出(NDRO)是可能的，从而提高读取周期的速度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Novel Merged Gain Cell For Logic Compatible High Density DRAMs

A new structured cell is proposed for the logic compatible Merged DRAM gain cell capable of reducing the cell size to almost one transistor area and with small increase in process steps. It can drastically improve “1” and “0” states separation due to the JFET effect of n channel region between two p+ gate regions. This new cell does not require new materials nor new equipments. Non-destructive read-out (NDRO) is possible resulting in higher speed read cycle.

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1997 Symposium on VLSI Technology

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