K. Yamaguchi, H. Nanbu, K. Kanetani, N. Homma, T. Nakamura, K. Ohhata, A. Uchida, K. Ogiue
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引用次数: 8
摘要
研制了一种实验性的64 kb 3-ns射极耦合逻辑随机存取存储器(RAM)。其关键因素是:软错误免疫存储单元，向上晶体管解码器，先进放电电路的达灵顿字驱动，0.8 μ m SICOS技术。为了减小存储单元的尺寸，高、低负载电阻器采用双层多晶硅。这些双层多晶硅对于实现498 μ m/sup /的存储单元尺寸至关重要。
An experimental soft-error immune 64-Kb 3 ns ECL bipolar RAM
An experimental soft-error immune 64-kb 3-ns emitter couple logic (ECL) random access memory (RAM) has been developed. Its key factors are: a soft-error immune memory cell, an upward transistor decoder, a Darlington word driver with advanced discharge circuits, and 0.8 mu m SICOS technology. To reduce the memory cell size, double-layer polysilicon is used for high and low load-resistor. These double layers of polysilicon are essential in realizing the memory cell size of 498 mu m/sup 2/.<>
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