基于ntt的多项式乘法器模减单元的实现

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI:10.1109/ISOCC50952.2020.9332926

Seungho Lee, Youngmin Kim

{"title":"基于ntt的多项式乘法器模减单元的实现","authors":"Seungho Lee, Youngmin Kim","doi":"10.1109/ISOCC50952.2020.9332926","DOIUrl":null,"url":null,"abstract":"This paper suggests the efficient implementation of Modular Subtraction Unit for NTT-based polynomial multiplier on ASIC design. We will introduce the basic algorithms of Number Theoretic Transform (NTT) and the Modular Arithmetic briefly, compare the implementation of the modular subtraction unit with the one which suggested in [1] by intuitive way. We reduced about 30% transistors in 17-bit Modular Subtraction Unit.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Implementation of Modular Subtraction Unit for NTT-based Polynomial Multiplier\",\"authors\":\"Seungho Lee, Youngmin Kim\",\"doi\":\"10.1109/ISOCC50952.2020.9332926\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper suggests the efficient implementation of Modular Subtraction Unit for NTT-based polynomial multiplier on ASIC design. We will introduce the basic algorithms of Number Theoretic Transform (NTT) and the Modular Arithmetic briefly, compare the implementation of the modular subtraction unit with the one which suggested in [1] by intuitive way. We reduced about 30% transistors in 17-bit Modular Subtraction Unit.\",\"PeriodicalId\":270577,\"journal\":{\"name\":\"2020 International SoC Design Conference (ISOCC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC50952.2020.9332926\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC50952.2020.9332926","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文提出了基于ntt的多项式乘法器的模块化减法单元在ASIC设计中的高效实现。本文将简要介绍数论变换(NTT)和模算法的基本算法，并将模减法单元的实现与文献[1]中提出的实现进行直观的比较。我们在17位模块减法单元中减少了大约30%的晶体管。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Implementation of Modular Subtraction Unit for NTT-based Polynomial Multiplier

This paper suggests the efficient implementation of Modular Subtraction Unit for NTT-based polynomial multiplier on ASIC design. We will introduce the basic algorithms of Number Theoretic Transform (NTT) and the Modular Arithmetic briefly, compare the implementation of the modular subtraction unit with the one which suggested in [1] by intuitive way. We reduced about 30% transistors in 17-bit Modular Subtraction Unit.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2020 International SoC Design Conference (ISOCC)

自引率

0.00%

发文量