{"title":"用于超大规模集成电路设计的时序数据库","authors":"Gregory Schulte, P. Tong, S. Rusu, Stuart Taylor","doi":"10.1109/EURDAC.1993.410672","DOIUrl":null,"url":null,"abstract":"A unified timing database for VLSI (very large scale integration) design is presented. The approach has been successfully used for the design of a three million transistor microprocessor. The database and timing methodology are oriented towards, but not restricted to, the top-down design style. Emphasis is placed upon integration with other timing tools such as circuit simulators, logic synthesis tools, and static timing analyzers.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"126 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"TONIC: A timing database for VLSI design\",\"authors\":\"Gregory Schulte, P. Tong, S. Rusu, Stuart Taylor\",\"doi\":\"10.1109/EURDAC.1993.410672\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A unified timing database for VLSI (very large scale integration) design is presented. The approach has been successfully used for the design of a three million transistor microprocessor. The database and timing methodology are oriented towards, but not restricted to, the top-down design style. Emphasis is placed upon integration with other timing tools such as circuit simulators, logic synthesis tools, and static timing analyzers.<<ETX>>\",\"PeriodicalId\":339176,\"journal\":{\"name\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"volume\":\"126 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-09-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1993.410672\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410672","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A unified timing database for VLSI (very large scale integration) design is presented. The approach has been successfully used for the design of a three million transistor microprocessor. The database and timing methodology are oriented towards, but not restricted to, the top-down design style. Emphasis is placed upon integration with other timing tools such as circuit simulators, logic synthesis tools, and static timing analyzers.<>
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