一种新型可编程增益放大器

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186148

G. O'Donoghue, M. Mallinson, P. Holloway

{"title":"一种新型可编程增益放大器","authors":"G. O'Donoghue, M. Mallinson, P. Holloway","doi":"10.1109/ASIC.1990.186148","DOIUrl":null,"url":null,"abstract":"A MOSFET input amplifier with variable gain from 0 to 42 dB and fixed bandwidth at all closed-loop gains is described. Designed for a system where phase match at all gains is the dominant design goal, this amplifier adapts its open-loop gain crossover point to keep a constant closed-loop gain. This is done by controlling an active matrix of PMOS input devices which simultaneously achieves the constant phase characteristic and optimizes the noise and offset performance. Eight such amplifiers are implemented on a single chip with more than 100 dB of isolation between each amplifier and a power supply rejection ratio (PSRR) of more than 70 dB from 0 to 30 kHz.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A novel programmable gain amplifier\",\"authors\":\"G. O'Donoghue, M. Mallinson, P. Holloway\",\"doi\":\"10.1109/ASIC.1990.186148\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A MOSFET input amplifier with variable gain from 0 to 42 dB and fixed bandwidth at all closed-loop gains is described. Designed for a system where phase match at all gains is the dominant design goal, this amplifier adapts its open-loop gain crossover point to keep a constant closed-loop gain. This is done by controlling an active matrix of PMOS input devices which simultaneously achieves the constant phase characteristic and optimizes the noise and offset performance. Eight such amplifiers are implemented on a single chip with more than 100 dB of isolation between each amplifier and a power supply rejection ratio (PSRR) of more than 70 dB from 0 to 30 kHz.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186148\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186148","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

描述了一种增益从0到42 dB可变的MOSFET输入放大器，在所有闭环增益下具有固定带宽。该放大器专为所有增益相位匹配为主要设计目标的系统而设计，其开环增益交叉点可保持恒定的闭环增益。这是通过控制PMOS输入器件的有源矩阵来实现的，该矩阵同时实现了恒相特性并优化了噪声和偏置性能。8个这样的放大器在单个芯片上实现，每个放大器之间的隔离度超过100 dB，电源抑制比(PSRR)在0到30 kHz范围内超过70 dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A novel programmable gain amplifier

A MOSFET input amplifier with variable gain from 0 to 42 dB and fixed bandwidth at all closed-loop gains is described. Designed for a system where phase match at all gains is the dominant design goal, this amplifier adapts its open-loop gain crossover point to keep a constant closed-loop gain. This is done by controlling an active matrix of PMOS input devices which simultaneously achieves the constant phase characteristic and optimizes the noise and offset performance. Eight such amplifiers are implemented on a single chip with more than 100 dB of isolation between each amplifier and a power supply rejection ratio (PSRR) of more than 70 dB from 0 to 30 kHz.<>

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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