在200mm GeOI晶圆上用Si工艺线制备高k和金属栅极的0.12μm p - mosfet

ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI:10.1109/ESSDERC.2007.4430977

C. Le Royer, L. Clavelier, C. Tabone, C. Deguet, L. Sanchez, J. Hartmann, M. Roure, H. Grampeix, S. Deleonibus

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引用次数: 13

摘要

摘要:我们首次报道了深亚微米(栅极长度低至0.12 μ m)的GeOI pmosfet。利用Smart-Cuttrade工艺将异质外延获得的Ge层转移到200 mm的GeOI晶片上，其Ge厚度降至60 nm。采用HfO2/TiN栅极堆栈实现了完全兼容CMOS的p-MOSFET工艺。制备器件的电学特性和测量性能(ION IOFF Gm, S, DIBL)的系统分析证明了GeOI上pMOSFET在先进技术节点上的潜力。

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0.12μm P-MOSFETs with High-K and Metal Gate Fabricated in a Si Process Line on 200mm GeOI Wafers

Abstract-For the first time, we report on deep sub-micron (gate length down to 0.12 mum) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart-Cuttrade process to fabricate 200 mm GeOI wafers with Ge thickness down to 60 nm. A full CMOS compatible p-MOSFET process was implemented with HfO2/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (ION IOFF Gm, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes.

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ESSDERC 2007 - 37th European Solid State Device Research Conference

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