串行保护应用的新型高压限流装置的设计和制造

J. Sanchez, P. Leturcq, P. Austin, R. Berriane, M. Breil, C. Anceau, C. Ayela
{"title":"串行保护应用的新型高压限流装置的设计和制造","authors":"J. Sanchez, P. Leturcq, P. Austin, R. Berriane, M. Breil, C. Anceau, C. Ayela","doi":"10.1109/ISPSD.1996.509481","DOIUrl":null,"url":null,"abstract":"This paper describes the design and fabrication of new two-terminal semiconductor devices, based on the concept of \"functional integration\", acting as current limiter for high voltage applications (400 V to 1,000 V). In the first section, the optimization of structures and fabrication processes are considered using 2D simulation tools SUPREM IV and PISCES. In the second section, the first experimental results of these devices are presented.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Design and fabrication of new high voltage current limiting devices for serial protection applications\",\"authors\":\"J. Sanchez, P. Leturcq, P. Austin, R. Berriane, M. Breil, C. Anceau, C. Ayela\",\"doi\":\"10.1109/ISPSD.1996.509481\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design and fabrication of new two-terminal semiconductor devices, based on the concept of \\\"functional integration\\\", acting as current limiter for high voltage applications (400 V to 1,000 V). In the first section, the optimization of structures and fabrication processes are considered using 2D simulation tools SUPREM IV and PISCES. In the second section, the first experimental results of these devices are presented.\",\"PeriodicalId\":377997,\"journal\":{\"name\":\"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-05-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.1996.509481\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1996.509481","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

摘要

本文描述了基于“功能集成”概念的新型双端半导体器件的设计和制造,作为高压应用(400 V至1,000 V)的限流器。在第一部分中,使用二维仿真工具SUPREM IV和PISCES考虑了结构和制造工艺的优化。在第二节中,给出了这些装置的初步实验结果。
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Design and fabrication of new high voltage current limiting devices for serial protection applications
This paper describes the design and fabrication of new two-terminal semiconductor devices, based on the concept of "functional integration", acting as current limiter for high voltage applications (400 V to 1,000 V). In the first section, the optimization of structures and fabrication processes are considered using 2D simulation tools SUPREM IV and PISCES. In the second section, the first experimental results of these devices are presented.
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