基于机器学习的扫描链故障诊断

Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang
{"title":"基于机器学习的扫描链故障诊断","authors":"Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang","doi":"10.1109/ISOCC50952.2020.9333074","DOIUrl":null,"url":null,"abstract":"In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-at fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Diagnosis of Scan Chain Faults Based-on Machine-Learning\",\"authors\":\"Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang\",\"doi\":\"10.1109/ISOCC50952.2020.9333074\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-at fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.\",\"PeriodicalId\":270577,\"journal\":{\"name\":\"2020 International SoC Design Conference (ISOCC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC50952.2020.9333074\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC50952.2020.9333074","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

为了提高纳米级芯片的成品率,基于扫描的测试和诊断是非常重要的。然而,由于扫描链本身所产生的庞大硬件占芯片总面积的相当大一部分,因此扫描链可能存在缺陷。因此,扫描链检测和诊断在近年来发挥了至关重要的作用。本文提出了一种基于两阶段神经网络的扫描链诊断方法,不仅适用于卡滞故障,也适用于过渡故障。在基准电路上的实验结果表明,该方法的准确率比以前的方法提高了10%,并且大大减少了神经网络的CPU训练时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Diagnosis of Scan Chain Faults Based-on Machine-Learning
In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-at fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A Quadcopters Flight Simulation Considering the Influence of Wind Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks Instant and Accurate Instance Segmentation Equipped with Path Aggregation and Attention Gate 13.56 MHz High-Efficiency Power Transmitter and Receiver for Wirelessly Powered Biomedical Implants Investigation on Synaptic Characteristics of Interfacial Phase Change Memory for Artificial Synapse Application
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1