{"title":"基于低变异性、高能耗、高面积效率忆阻器的组合逻辑电路","authors":"Shruti Sandip Ghodke, Sanjay Kumar, Saurabh Yadav, Narendra Singh Dhakad, Shaibal Mukherjee","doi":"10.1007/s10825-023-02117-6","DOIUrl":null,"url":null,"abstract":"<p>The saturation of complementary metal–oxide–semiconductor (CMOS) technology in terms of area and power efficiency has given rise to advanced research on nanodevices. Memristors and their switching properties facilitate the implementation of various combinational logics and neural networks by potential replacement of the existing CMOS technology for edge computing devices. This work presents the design, implementation, and performance evaluation of memristor-based combinational logic circuits including adders, subtractors, and decoders via MATLAB Simulink and Cadence Virtuoso. In this work, we propose an optimized design of memristor-based combinational logic circuits and conduct a comparative study with the conventional method. The proposed memristor model is thoroughly validated experimentally for a high-density Y<sub>2</sub>O<sub>3</sub>-based memristive crossbar array and shows ultralow values in device-to-device and cycle-to-cycle variability. The power calculated from these circuits is reduced by more than 90% as compared to conventional CMOS technology implemented in Cadence Virtuoso. Moreover, the number of components utilized in the memristor-based logic circuits is significantly reduced in comparison to existing CMOS technology, which makes it more area-efficient and opens new avenues for the design and implementation of complex logic circuitry in few-micrometer scale.</p>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":null,"pages":null},"PeriodicalIF":2.2000,"publicationDate":"2023-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Combinational logic circuits based on a power- and area-efficient memristor with low variability\",\"authors\":\"Shruti Sandip Ghodke, Sanjay Kumar, Saurabh Yadav, Narendra Singh Dhakad, Shaibal Mukherjee\",\"doi\":\"10.1007/s10825-023-02117-6\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p>The saturation of complementary metal–oxide–semiconductor (CMOS) technology in terms of area and power efficiency has given rise to advanced research on nanodevices. Memristors and their switching properties facilitate the implementation of various combinational logics and neural networks by potential replacement of the existing CMOS technology for edge computing devices. This work presents the design, implementation, and performance evaluation of memristor-based combinational logic circuits including adders, subtractors, and decoders via MATLAB Simulink and Cadence Virtuoso. In this work, we propose an optimized design of memristor-based combinational logic circuits and conduct a comparative study with the conventional method. The proposed memristor model is thoroughly validated experimentally for a high-density Y<sub>2</sub>O<sub>3</sub>-based memristive crossbar array and shows ultralow values in device-to-device and cycle-to-cycle variability. The power calculated from these circuits is reduced by more than 90% as compared to conventional CMOS technology implemented in Cadence Virtuoso. Moreover, the number of components utilized in the memristor-based logic circuits is significantly reduced in comparison to existing CMOS technology, which makes it more area-efficient and opens new avenues for the design and implementation of complex logic circuitry in few-micrometer scale.</p>\",\"PeriodicalId\":620,\"journal\":{\"name\":\"Journal of Computational Electronics\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2023-12-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Computational Electronics\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://doi.org/10.1007/s10825-023-02117-6\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Computational Electronics","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1007/s10825-023-02117-6","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Combinational logic circuits based on a power- and area-efficient memristor with low variability
The saturation of complementary metal–oxide–semiconductor (CMOS) technology in terms of area and power efficiency has given rise to advanced research on nanodevices. Memristors and their switching properties facilitate the implementation of various combinational logics and neural networks by potential replacement of the existing CMOS technology for edge computing devices. This work presents the design, implementation, and performance evaluation of memristor-based combinational logic circuits including adders, subtractors, and decoders via MATLAB Simulink and Cadence Virtuoso. In this work, we propose an optimized design of memristor-based combinational logic circuits and conduct a comparative study with the conventional method. The proposed memristor model is thoroughly validated experimentally for a high-density Y2O3-based memristive crossbar array and shows ultralow values in device-to-device and cycle-to-cycle variability. The power calculated from these circuits is reduced by more than 90% as compared to conventional CMOS technology implemented in Cadence Virtuoso. Moreover, the number of components utilized in the memristor-based logic circuits is significantly reduced in comparison to existing CMOS technology, which makes it more area-efficient and opens new avenues for the design and implementation of complex logic circuitry in few-micrometer scale.
期刊介绍:
he Journal of Computational Electronics brings together research on all aspects of modeling and simulation of modern electronics. This includes optical, electronic, mechanical, and quantum mechanical aspects, as well as research on the underlying mathematical algorithms and computational details. The related areas of energy conversion/storage and of molecular and biological systems, in which the thrust is on the charge transport, electronic, mechanical, and optical properties, are also covered.
In particular, we encourage manuscripts dealing with device simulation; with optical and optoelectronic systems and photonics; with energy storage (e.g. batteries, fuel cells) and harvesting (e.g. photovoltaic), with simulation of circuits, VLSI layout, logic and architecture (based on, for example, CMOS devices, quantum-cellular automata, QBITs, or single-electron transistors); with electromagnetic simulations (such as microwave electronics and components); or with molecular and biological systems. However, in all these cases, the submitted manuscripts should explicitly address the electronic properties of the relevant systems, materials, or devices and/or present novel contributions to the physical models, computational strategies, or numerical algorithms.