锥形氧化硅蚀刻用于创建电容器结构以测量介电特性

Q4 Engineering Russian Microelectronics Pub Date : 2024-02-08 DOI:10.1134/s1063739723700695
A. V. Miakonkikh, V. O. Kuzmenko, A. E. Melnikov, K. V. Rudenko
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引用次数: 0

摘要

摘要 文章探讨了使用干法蚀刻方法形成具有锥形壁的氧化硅结构的可能性,包括形成锥形光刻胶掩膜和等离子体蚀刻氧化硅的两阶段过程。对锥形抗蚀剂蚀刻过程进行了研究。研究了等离子体参数和成分对蚀刻过程的影响,使用朗缪尔探针和光发射光度法进行了等离子体诊断,并提出了锥形抗蚀剂蚀刻的机理。对蚀刻过程进行了优化,获得了抗蚀剂厚度为 400 nm、侧壁角度高达 61° 的结构。随后的二氧化硅蚀刻过程可以转移抗蚀剂的斜率。二氧化硅壁的斜度为 57°。由此产生的具有锥形二氧化硅壁的结构可以制作电容器,用于研究电介质的特性以及微机电和微流体的结构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

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Tapered Silicon Oxide Etching for Creation of Capacitor Structures for Measurement of Dielectric Characteristics

Abstract

The article develops the possibility of forming silicon oxide structures with tapered walls using dry etching methods, including a two-stage process involving the formation of a tapered photoresist mask and plasma etching of the silicon oxide. A study of the process of tapered resist etching was carried out. The influence of plasma parameters and composition on the etching process was studied, plasma diagnostics were carried out using Langmuir probe and optical emission actinometry methods, and the mechanisms of tapered resist etching were suggested. The etching process was optimized and structures with a resist thickness of 400 nm and a sidewall angle of up to 61° were obtained. A subsequent SiO2 etching process allowed the slope of the resist to be transferred. The slope of the SiO2 wall was 57°. The resulting structures with tapered SiO2 walls make it possible to produce capacitors for studying the characteristics of dielectrics, as well as the structure of microelectromechanics and microfluidics.

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来源期刊
Russian Microelectronics
Russian Microelectronics Materials Science-Materials Chemistry
CiteScore
0.70
自引率
0.00%
发文量
43
期刊介绍: Russian Microelectronics  covers physical, technological, and some VLSI and ULSI circuit-technical aspects of microelectronics and nanoelectronics; it informs the reader of new trends in submicron optical, x-ray, electron, and ion-beam lithography technology; dry processing techniques, etching, doping; and deposition and planarization technology. Significant space is devoted to problems arising in the application of proton, electron, and ion beams, plasma, etc. Consideration is given to new equipment, including cluster tools and control in situ and submicron CMOS, bipolar, and BICMOS technologies. The journal publishes papers addressing problems of molecular beam epitaxy and related processes; heterojunction devices and integrated circuits; the technology and devices of nanoelectronics; and the fabrication of nanometer scale devices, including new device structures, quantum-effect devices, and superconducting devices. The reader will find papers containing news of the diagnostics of surfaces and microelectronic structures, the modeling of technological processes and devices in micro- and nanoelectronics, including nanotransistors, and solid state qubits.
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