Russian Microelectronics最新文献

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Thermal Modeling and Layout Optimization of GaN Half-Bridge IC with Integrated Drivers and Power HEMTs 集成驱动器和功率 HEMT 的氮化镓半桥集成电路的热建模和布局优化

Q4 Engineering

Russian Microelectronics

Pub Date : 2024-07-26 DOI: 10.1134/s1063739724600225

V. A. Kagadey, I. Y. Kodorova, E. S. Polyntsev

Abstract

The paper presents the results of thermal modeling of a half-bridge monolithic integrated circuit (IC) with integrated drivers and enhanced mode power high electron mobility transistors, based on a GaN-on-SOI heterostructure. It had been established that the main heat sources in the IC were the half-bridge GaN HEMTs. The heat from the half-bridge GaN HEMTs propagates in the chip and leads to heating of the logic block and gate drivers. Heating of half-bridge GaN HEMTs leads to increased channel resistance and IC output current drop. Heating of the gate drivers reduces driving current, as a result, increases the switching time of the half-bridge GaN HEMTs. Heating of the logic block increases the rise and fall times of the generated control signals, which worsens the dynamic characteristics of the IC. A comparative analysis of heat propagation for IC dies based on GaN-on-SOI and GaN-on-Si heterostructures showed that GaN-on-SOI structure has a 40% greater junction-to-backside thermal resistivity compared to GaN-on-Si structure. In this case, the specific thermal resistance in the direction of heat propagation from the hotspot of the transistor to the backside of the die for the GaN-on-SOI structure is almost two orders of magnitude greater than in the direction of its propagation to the frontside of the chip. The results obtained were used for IC layout optimization. The rearrangement of GaN-on-SOI IC functional blocks, as well as to introduction of additional heat-spreading elements on the frontside of chip were carried out during the optimization.

摘要本文介绍了基于 GaN-on-SOI 异质结构、集成了驱动器和增强型功率高电子迁移率晶体管的半桥单片集成电路（IC）的热建模结果。已确定集成电路中的主要热源是半桥 GaN HEMT。来自半桥 GaN HEMT 的热量在芯片中传播，导致逻辑块和栅极驱动器发热。半桥氮化镓 HEMT 的发热会导致通道电阻增加和集成电路输出电流下降。栅极驱动器发热会降低驱动电流，从而延长半桥 GaN HEMT 的开关时间。逻辑块发热会增加生成的控制信号的上升和下降时间，从而使集成电路的动态特性恶化。对基于硅基氮化镓和硅基氮化镓异质结构的集成电路芯片进行的热传播比较分析表明，硅基氮化镓结构的结至背面热阻比硅基氮化镓结构高 40%。在这种情况下，GaN-on-SOI 结构从晶体管热点到芯片背面的热传播方向上的比热阻几乎比向芯片正面传播方向上的比热阻大两个数量级。所得结果用于集成电路布局优化。在优化过程中，对硅基氮化镓集成电路功能块进行了重新排列，并在芯片正面引入了额外的散热元件。

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引用次数: 0

Design a Configurable First Order Universal Filter Using a Single EX-CCCII 使用单个 EX-CCCII 设计可配置的一阶通用滤波器

Q4 Engineering

Russian Microelectronics

Pub Date : 2024-07-26 DOI: 10.1134/s1063739724600080

Deepak Agrawal, Shailendra K. Tripathi, N Soma Sekhar Reddy, M. Sai Vineeth Reddy, P. Mohammad Shoaib

Abstract

In this work, a single active element (Extra-X Current Controlled Conveyor) with grounded capacitor is used to design a reconfigurable first-order universal filter (CFUF). By simply swapping the digital control words (k₁k₂), the suggested circuit may implement all of the common filter responses, including high-pass, low-pass, and all-pass. An EX-CCCII serves as the active element in the filter setup, which is based on a novel topology, which provides several advantages, such as reduced complexity, low power consumption, and improved performance. The following advantages of the proposed circuit: high input impedance for voltage input signals, electronically controllable pole frequency that varies with bias current, and a single grounded capacitor that can be integrated into an IC. At a power supply level of ±0.5 V, the proposed circuit is modeled using specifications for 0.18-micrometer CMOS technology. PSPICE simulation tool is used to demonstrate the filter’s performance.

摘要在这项研究中，我们利用带有接地电容器的单个有源元件（Extra-X 电流控制传送带）设计了一种可重新配置的一阶通用滤波器（CFUF）。通过简单地交换数字控制字（k1k2），所建议的电路可以实现所有常见的滤波器响应，包括高通、低通和全通。EX-CCCII 作为滤波器设置中的有源元件，基于新颖的拓扑结构，具有降低复杂性、低功耗和提高性能等优点。该电路具有以下优点：电压输入信号的输入阻抗高；极点频率可随偏置电流变化而进行电子控制；只需一个接地电容器即可集成到集成电路中。在 ±0.5 V 的电源电平下，建议的电路采用 0.18 微米 CMOS 技术规格建模。PSPICE 仿真工具用于演示滤波器的性能。

引用次数: 0

Influence of Laser Radiation on Functional Properties MOS Device Structures 激光辐射对 MOS 器件结构功能特性的影响

Q4 Engineering

Russian Microelectronics

Pub Date : 2024-07-26 DOI: 10.1134/s1063739724600262

S. Sh. Rekhviashvili, D. S. Gaev

Abstract

The electrical and physical properties of MOS device structures (capacitor, field-effect transistor with an insulated gate and induced channel, CMOS integrated circuit) when exposed to unmodulated laser radiation are studied. The static and dynamic characteristics are measured. The theoretical study is carried out using the developed SPICE models and numerical experiments. An expression is obtained for the volt-ampere characteristics (VACs) of a field-effect transistor operating in a mode with constant optical illumination. It is shown that the characteristics of structures are determined by the generation and recombination of nonequilibrium charge carriers, the field effect, and the photovoltaic effect in p–n-junctions, the Dember effect, and the tunneling of charge carriers through the gate dielectric. The results of the study are of interest in terms of creating high-speed transistors and integrated circuits of a new type.

摘要研究了 MOS 器件结构（电容器、具有绝缘栅极和感应沟道的场效应晶体管、CMOS 集成电路）在未调制激光辐射下的电气和物理特性。测量了静态和动态特性。理论研究使用开发的 SPICE 模型和数值实验进行。获得了在恒定光照模式下工作的场效应晶体管的伏安特性 (VAC) 表达式。研究表明，非平衡电荷载流子的产生和重组、场效应、p-n 结中的光电效应、邓伯效应以及电荷载流子通过栅极电介质的隧道效应决定了晶体管结构的特性。研究结果对制造新型高速晶体管和集成电路具有重要意义。

引用次数: 0

Analysis of Carrier Scattering Mechanisms in AlN/GaN HEMT Heterostructures with an Ultrathin AlN Barrier 带有超薄氮化铝势垒的氮化铝/氮化镓 HEMT 异质结构中的载流子散射机制分析

Q4 Engineering

Russian Microelectronics

Pub Date : 2024-07-26 DOI: 10.1134/s1063739724600304

A. S. Gusev, A. O. Sultanov, A. V. Katkov, S. M. Ryndya, N. V. Siglovaya, A. N. Klochkov, R. V. Ryzhuk, N. I. Kargin, D. P. Borisenko

Abstract

Using the method of molecular beam epitaxy with the plasma activation of nitrogen, experimental AlN/GaN heterostructures (HSs) with an ultrathin AlN barrier are obtained. The layer resistance of the optimized structures is less than 230 Ω/□. The scattering processes that limit the mobility of a two-dimensional electron gas (2DEG) in undoped AlN/GaN HSs with an ultrathin AlN barrier are studied. It is shown that in the range of n_s characteristic for AlN/GaN HEMT HSs (n_s > 1 × 10¹³ cm^–2), a noticeable contribution to the scattering of charge carriers is made by the roughness of the heterointerface.

摘要利用分子束外延和氮等离子活化的方法，获得了具有超薄氮化铝阻挡层的氮化铝/氮化镓异质结构（HS）。优化结构的层电阻小于 230 Ω/□。研究了限制具有超薄氮化铝势垒的未掺杂氮化铝/氮化镓 HS 中二维电子气体（2DEG）迁移率的散射过程。研究表明，在 AlN/GaN HEMT HS 的 ns 特性范围内（ns > 1 × 1013 cm-2），异质表面的粗糙度对电荷载流子的散射有明显的贡献。

引用次数: 0

How Memristor Device Records Memory Signal: Electromagnetic Study through an Equivalent Setup Memristor 器件如何记录记忆信号：通过等效设置进行电磁研究

Q4 Engineering

Russian Microelectronics

Pub Date : 2024-07-26 DOI: 10.1134/s1063739724600043

Hassan Ali

Abstract

Memristor is an electronic device, which corresponds to a switch translating memory data (synapse) into resistance values. Scientists made a switch with a combination of titanium dioxide (Tio₂) and oxygen deficient TiO₂ to create a metal-insulator transition mechanism to make a device with nonlinear conductive states R_on and R_off. This work presents the memory storing capability of memristor by utilizing an equivalent experimental setup of steel balls array. An experiment exhibits an identical memristive mechanism of memristor device where the nonlinear conductive states along an array of steel balls describes an exact mechanism of memristor’s functionality. Via utilizing an identical setup, we depict electric and magnetic field compatibility at memristor’s pinched (_{on & off}) regions. It shows that how memristor stores synaptic information by means of resistance values at its pinched (_{on & off}) conducting regions. The aim of this effort is to provide technical support to conceive a memristor as a resistive memory storage device, which changes its resistance values with respect to applied voltage (multiple synaptic weights).

摘要晶闸管是一种电子装置，相当于将记忆数据（突触）转化为电阻值的开关。科学家们用二氧化钛（Tio2）和缺氧二氧化钛（TiO2）的组合制造了一个开关，创造了一种金属-绝缘体转换机制，从而制造出具有非线性导电状态的器件罗恩和罗夫。这项研究利用钢球阵列的等效实验装置，展示了忆阻器的记忆存储能力。实验展示了忆阻器装置的相同记忆机制，其中沿着钢球阵列的非线性导电状态描述了忆阻器功能的确切机制。通过利用相同的装置，我们描绘了忆阻器捏合（开& 关）区域的电场和磁场兼容性。它显示了忆阻器是如何通过其夹（开和关）导电区域的电阻值来存储突触信息的。这项工作的目的是为将忆阻器视为电阻式记忆存储设备提供技术支持，忆阻器的电阻值会随外加电压的变化而变化（多重突触权重）。

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引用次数: 0

Simulation of Silicon Field-Effect Conical GAA Nanotransistors with a Stacked SiO2/HfO2 Subgate Dielectric 带有叠层 SiO2/HfO2 亚门电介质的硅场效应锥形 GAA 纳米晶体管仿真

Q4 Engineering

Russian Microelectronics

Pub Date : 2024-07-26 DOI: 10.1134/s1063739724600274

N. V. Masal’skii

Abstract

The issues of modeling the electrical characteristics of a silicon conical field-effect gate-all-around (GAA) nanotransistor are discussed. An analytical model of the drain current of a transistor with a fully encompassing conical gate with a stacked subgate SiO₂/HfO₂ oxide, taking into account the influence of the charge of the interfacial trap at the Si/SiO₂ interface, is developed. To model the potential distribution in a conical working area under the condition of a constant trap density, an analytical solution of the Poisson equation is obtained using the parabolic approximation method in the cylindrical coordinate system with the corresponding boundary conditions. The potential model is used to develop an expression for the drain current of a GAA nanotransistor with a stacked subgate oxide. The key electrical and physical characteristics are numerically studied depending on the density of the traps and the thickness of the SiO₂ and HfO₂ layers.

摘要讨论了硅锥形场效应栅全围（GAA）纳米晶体管电气特性的建模问题。考虑到硅/二氧化硅界面上的界面陷阱电荷的影响，建立了一个具有完全包覆锥形栅极和堆叠子栅极 SiO2/HfO2 氧化物的晶体管漏极电流的分析模型。为了模拟陷阱密度恒定条件下锥形工作区的电势分布，在圆柱坐标系中使用抛物线近似法得到了泊松方程的解析解，并给出了相应的边界条件。利用该势垒模型，我们得出了具有叠层亚门氧化物的 GAA 纳米晶体管漏极电流的表达式。根据阱的密度以及二氧化硅层和二氧化铪层的厚度，对关键的电气和物理特性进行了数值研究。

引用次数: 0

Structure and Formation of Superflash Nonvolatile Memory Cells 超级闪存非易失性存储器单元的结构与形成

Q4 Engineering

Russian Microelectronics

Pub Date : 2024-07-26 DOI: 10.1134/s1063739724600249

D. A. Abdullaev, E. V. Bobrova, R. A. Milovanov

Abstract

Split-gate embedded Flash memory technology has been around for decades and has become the standard application for a wide range of devices such as microcontrollers and smart cards. Among them, due to a number of advantages, SuperFlash (SF) produced by Silicon Storage Technology is the most widely used nonvolatile memory technology. In this paper, the results of a study of the structure of memory cells (MCs) are presented and the principle of their operation, as well as the main technological stages of the production process of forming transistor structures, is discussed.

摘要分路栅极嵌入式闪存技术已有几十年的历史，已成为微控制器和智能卡等多种设备的标准应用。其中，硅存储技术公司（Silicon Storage Technology）生产的超级闪存（SuperFlash，SF）因其诸多优点而成为应用最广泛的非易失性存储器技术。本文介绍了存储单元（MC）结构的研究成果，并讨论了其工作原理以及形成晶体管结构的生产过程的主要技术阶段。

引用次数: 0

A Comprehensive Study of Nonuniformity Properties of the LiCoO2 Thin-Film Cathode Fabricated by RF Sputtering 射频溅射法制造的钴酸锂薄膜阴极的非均匀性综合研究

Q4 Engineering

Russian Microelectronics

Pub Date : 2024-07-26 DOI: 10.1134/s1063739724600250

S. V. Kurbatov, A. S. Rudy, V. V. Naumov, A. A. Mironenko, O. V. Savenko, M. A. Smirnova, L. A. Mazaletsky, D. E. Pukhov

Abstract

The influence of nonuniformity properties of the LiCoO₂ cathode film deposited by magnetron sputtering on the capacity of all-solid-state thin-film lithium-ion batteries (ASSLIB) was studied. It was found that the film nonuniformity corresponds to the magnetron plasma density distribution and the angular distribution of sputtered particles. The capacity distribution of the ASSLIB with LiCoO₂ cathode depending on the distance to the substrate center was studied. The maximum capacity corresponded to the dense part of the toroidal region of the magnetron plasma. It was determined that the main causes of batteries capacity decline in the central part and on the edge of the substrate are the impurity phase of lithium cobaltate and the smaller thickness of the cathode layer, respectively.

摘要研究了磁控溅射沉积钴酸锂正极薄膜的不均匀性对全固态薄膜锂离子电池（ASSLIB）容量的影响。研究发现，薄膜的不均匀性与磁控管等离子体密度分布和溅射粒子的角度分布相对应。研究了带有钴酸锂阴极的 ASSLIB 的容量分布，它取决于到衬底中心的距离。最大容量与磁控管等离子体环形区域的密集部分相对应。结果表明，电池容量在基板中心和边缘下降的主要原因分别是钴酸锂的杂质相和阴极层厚度较小。

引用次数: 0

Kinetics of Electromigration Mass Transfer in the Interface Elements of Micro- and Nanoelectronics Depending on the Strength of Thin-Film Connections 取决于薄膜连接强度的微电子和纳米电子学界面元件中的电迁移传质动力学

Q4 Engineering

Russian Microelectronics

Pub Date : 2024-07-26 DOI: 10.1134/s1063739724600286

T. M. Makhviladze, M. E. Sarychev

Abstract

This study improves and expands the scope of application of the theoretical model previously proposed by the authors, which describes the relationship between the strength and electromigration (diffusion) properties of interfaces formed by connected materials. In the developed model, a linear relationship is established between the values of the work of reversible interface separation ({{W}_{a}}) and electromigration activation energy ({{H}_{{EM}}}) in the interface. Estimates are made and the coefficients of the resulting relation are compared with experiments studying electromigration in a copper conductor coated with a protective dielectric. Using also the model previously developed by the authors, which describes the dependence of the quantity ({{W}_{a}}) on the concentrations of nonequilibrium lattice defects presenting in the volumes of connected materials, a number of effects due to the influence of such defects on processes caused by electromigration are predicted and studied. This study shows that by introducing nonequilibrium lattice defects in the form of atomic interstitial or substitutional impurities into the volumes of the joined materials, we can effectively influence on the characteristics of the electromigration instability of the shape of the interlayer boundary. For interstitial impurities, quantitative analytical estimates of the impurity concentration required to significantly change (both increase and decrease) the characteristic growth time of the instability of the shape of an initially flat interface are performed.

摘要本研究改进并扩大了作者之前提出的理论模型的应用范围，该模型描述了由相连材料形成的界面的强度和电迁移（扩散）特性之间的关系。在所建立的模型中，界面中可逆界面分离功（{{W}_{a}}/）和电迁移活化能（{{H}_{EM}}}/）的值之间建立了线性关系。我们进行了估算，并将所得关系的系数与铜导体上涂有保护电介质的电迁移实验进行了比较。该模型描述了 ({{W}_{a}})量对连接材料体积中出现的非平衡晶格缺陷浓度的依赖性，同时还使用了作者之前开发的模型，预测并研究了由于这些缺陷对电迁移过程的影响而产生的一系列效应。研究表明，通过在连接材料的体积中引入原子间隙或置换杂质形式的非平衡晶格缺陷，我们可以有效地影响层间边界形状的电迁移不稳定性特征。对于间隙杂质，我们对显著改变（增加和减少）初始平坦界面形状不稳定性特征生长时间所需的杂质浓度进行了定量分析估算。

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引用次数: 0

Development of a Ge-MISFET Instrument Structure with an Induced p-Type Channel 开发具有诱导 p 型沟道的 Ge-MISFET 仪器结构

Q4 Engineering

Russian Microelectronics

Pub Date : 2024-07-26 DOI: 10.1134/s1063739724600298

N. A. Alyabina, E. A. Arkhipova, Yu. N. Buzynin, S. A. Denisov, A. V. Zdoroveishchev, A. M. Titova, V. Yu. Chalkov, V. G. Shengurov

Abstract

The conditions for the growth of n-type Ge layers with the parameters required to create a Ge-MISFET with an induced p-type channel using the hot wire chemical vapor deposition (HW CVD) method are determined. The conditions for deposition using electron beam deposition and subsequent annealing of the subgate high-k dielectric ZrO₂:Y₂O₃ layers are optimized, allowing us to achieve a leakage current value of 5 × 10^–6 A/cm². For the developed device structure, some parameters of the Ge-MISFET are calculated, such as the channel length, maximum voltage between the sink and source, and breakdown voltage.

摘要确定了采用热线化学气相沉积（HW CVD）方法生长具有所需参数的 n 型 Ge 层的条件，以制造具有诱导 p 型沟道的 Ge-MISFET。优化了电子束沉积的沉积条件以及次栅极高介电质 ZrO2:Y2O3 层的退火条件，使我们的漏电流值达到 5 × 10-6 A/cm2。针对所开发的器件结构，我们计算了 Ge-MISFET 的一些参数，如沟道长度、沉源之间的最大电压和击穿电压。

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全部化学•材料生命科学医学物理工程技术环境•农林材料科学地球科学法学管理学化学环境科学与生态学计算机科学教育学经济学农林科学人文科学生物学数学物理与天体物理心理学综合性期刊其他工业工程理学历史学农学文学信息工程

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Russian Microelectronics

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