并联 SiC MOSFET 断路器与用于雪崩电压钳位的 SiC MPS 二极管

IF 5 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE open journal of power electronics Pub Date : 2024-02-14 DOI:10.1109/OJPEL.2024.3365830
Taro Takamori;Keiji Wada;Wataru Saito;Shin-ichi Nishizawa
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引用次数: 0

摘要

本文基于雪崩电压箝位原理,提出了一种由碳化硅 (SiC) MOSFET 和 SiC 二极管组成的固态断路器。实现固态断路器的关键挑战在于降低传导损耗。功率半导体器件的并联是能够满足这些要求的合适配置。然而,在这种配置中,截止操作期间的电流平衡可能会受到功率半导体器件击穿电压特性变化的影响。为解决这一问题,所提出的断路器采用了碳化硅合并引脚肖特基(MPS)二极管箝位,该二极管具有较高的雪崩容限和在重复雪崩事件下的稳健特性。通过在使用 400 V、50 A 直流配电系统的非箝位感应开关(UIS)测试电路中进行实验,验证了所提出的固态断路器的有效性。最终,演示结果表明,SiC 二极管箝位方法有助于固态断路器更紧凑的实现。
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Paralleled SiC MOSFETs Circuit Breaker With a SiC MPS Diode for Avalanche Voltage Clamping
This paper proposes a solid-state circuit breaker comprising silicon carbide (SiC) MOSFETs and a SiC diode, based on the principle of avalanche voltage clamping. The key challenge in realizing a solid-state circuit breaker lies in reducing conduction loss. A parallel connection of power semiconductor devices is the suitable configuration that can meet these requirements. However, in such a configuration, the current balance during cutoff operation may be affected by the variation in the breakdown voltage characteristics of the power semiconductor devices. To address this issue, the proposed circuit breaker employs clamping with a SiC merged pin Schottky (MPS) diode, with high avalanche tolerance and robust characteristics under repetitive avalanche events. The effectiveness of the proposed solid-state circuit breaker is validated through experiments conducted in an unclamped inductive switching (UIS) test circuit using a 400-V, 50-A DC distribution system. Eventually, the demonstrations indicate that the SiC diode clamping method contributes to more compact implementations for solid-state circuit breakers.
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8.60
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审稿时长
8 weeks
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