This work presents an efficiency-oriented modulation and morphing strategy for a three-phase three-level dual active bridge converter operating across both 800 V and 400 V electric vehicle battery systems. By reconfiguring the converter into a single-phase dual active bridge or a hybrid half-bridge/full-bridge structure at light-load, the proposed approach reduces current-invariant losses. A unified dual phase-shift framework is formulated to analytically model power flow and peak-current minimization across all three-level modulation variants, inner phase shift, duty-cycle control, and T-type zero-level modulation, demonstrating that all combinations produce equivalent voltage and current waveforms. Simulation efficiency maps are generated for all valid primary/secondary modulation pairs and indicate that inner and duty-cycle modulation achieve the highest efficiency across the full operating window. Hardware-in-the-loop experiments confirm stable three-phase-to-single-phase morphing and accurate power tracking between reference and measured power profiles for both voltage levels. The results validate that the proposed morphing strategy enables wide-range, auxiliary-free light-load operation suitable for next-generation EV charging architectures.
{"title":"Efficiency-Oriented DPS Implementation in Morphed Three-Phase Three-Level DAB for Light-Load EV Charging","authors":"Lohith Kumar Pittala;Francesca Grazian;Jiayi Geng;Gabriele Rizzoli;George Papafotiou;Mattia Ricco;Riccardo Mandrioli","doi":"10.1109/OJPEL.2026.3656043","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3656043","url":null,"abstract":"This work presents an efficiency-oriented modulation and morphing strategy for a three-phase three-level dual active bridge converter operating across both 800 V and 400 V electric vehicle battery systems. By reconfiguring the converter into a single-phase dual active bridge or a hybrid half-bridge/full-bridge structure at light-load, the proposed approach reduces current-invariant losses. A unified dual phase-shift framework is formulated to analytically model power flow and peak-current minimization across all three-level modulation variants, inner phase shift, duty-cycle control, and T-type zero-level modulation, demonstrating that all combinations produce equivalent voltage and current waveforms. Simulation efficiency maps are generated for all valid primary/secondary modulation pairs and indicate that inner and duty-cycle modulation achieve the highest efficiency across the full operating window. Hardware-in-the-loop experiments confirm stable three-phase-to-single-phase morphing and accurate power tracking between reference and measured power profiles for both voltage levels. The results validate that the proposed morphing strategy enables wide-range, auxiliary-free light-load operation suitable for next-generation EV charging architectures.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"397-408"},"PeriodicalIF":3.9,"publicationDate":"2026-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11359460","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-16DOI: 10.1109/OJPEL.2026.3654526
Yousef H. Abudyak;Mohammad Hossein Rezaei;Ahmad A. Bany Abdelnabi;Houshang Salimian Rizi;Issa Batarseh;Alex Q. Huang
The rapid growth of Renewable Energy (RE) resources intensifies stability challenges due to their intermittency, especially in grids with low Short-Circuit Ratios (SCRs). Grid-Forming (GFM) inverters have gained prominence as a promising solution to these challenges, in contrast to Grid-Following (GFL) inverters that often fail to maintain synchronism. This review provides a structured synthesis of the existing literature on GFM inverters, with emphasis on control philosophies, stability perspectives, and conceptual frameworks that guide their application. It further discusses emerging themes such as the integration of Artificial Intelligence (AI) and Digital Twins (DTs), reflecting their growing relevance in shaping. future research directions. Recent project experiences and industry developments are also reviewed to situate GFMs within broader market and deployment contexts. By consolidating diverse viewpoints and offering comparative insights, this paper serves as a reference for researchers and practitioners seeking to understand and advance the role of GFMs in renewable-rich power systems.
{"title":"Grid-Forming Inverters Review: Control, Stability, and the Next Stage With Artificial Intelligence and Digital Twins","authors":"Yousef H. Abudyak;Mohammad Hossein Rezaei;Ahmad A. Bany Abdelnabi;Houshang Salimian Rizi;Issa Batarseh;Alex Q. Huang","doi":"10.1109/OJPEL.2026.3654526","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3654526","url":null,"abstract":"The rapid growth of Renewable Energy (RE) resources intensifies stability challenges due to their intermittency, especially in grids with low Short-Circuit Ratios (SCRs). Grid-Forming (GFM) inverters have gained prominence as a promising solution to these challenges, in contrast to Grid-Following (GFL) inverters that often fail to maintain synchronism. This review provides a structured synthesis of the existing literature on GFM inverters, with emphasis on control philosophies, stability perspectives, and conceptual frameworks that guide their application. It further discusses emerging themes such as the integration of Artificial Intelligence (AI) and Digital Twins (DTs), reflecting their growing relevance in shaping. future research directions. Recent project experiences and industry developments are also reviewed to situate GFMs within broader market and deployment contexts. By consolidating diverse viewpoints and offering comparative insights, this paper serves as a reference for researchers and practitioners seeking to understand and advance the role of GFMs in renewable-rich power systems.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"351-387"},"PeriodicalIF":3.9,"publicationDate":"2026-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11355925","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-12DOI: 10.1109/OJPEL.2026.3653481
Zhoulong Wang;Li Zhang
In wide input range and high step-down application, conventional Sigma converter suffers from the problem of small duty cycle and low efficiency of the internal Buck converter. A stacked half-bridge (SHB)-based Sigma-type topology has been proposed by integrating an LLC resonant converter and a Buck converter with an SHB structure, which inherently halves the input voltage for the LLC and Buck converter. Compared with the conventional Sigma topology, the proposed topology achieves higher efficiency under the same gain and power distribution conditions, due to the optimized duty cycle range of the Buck converter. Besides, all switches in the SHB achieve ZVS through phase-shift control, effectively reducing switching losses. An experimental prototype with 42-55V input and 5 V/80 W output is built, demonstrating a peak efficiency of 95.1% .
{"title":"High-Efficiency Stacked Half-Bridge Sigma Topology for Wide Input Range and High Step-Down Application","authors":"Zhoulong Wang;Li Zhang","doi":"10.1109/OJPEL.2026.3653481","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3653481","url":null,"abstract":"In wide input range and high step-down application, conventional Sigma converter suffers from the problem of small duty cycle and low efficiency of the internal Buck converter. A stacked half-bridge (SHB)-based Sigma-type topology has been proposed by integrating an LLC resonant converter and a Buck converter with an SHB structure, which inherently halves the input voltage for the LLC and Buck converter. Compared with the conventional Sigma topology, the proposed topology achieves higher efficiency under the same gain and power distribution conditions, due to the optimized duty cycle range of the Buck converter. Besides, all switches in the SHB achieve ZVS through phase-shift control, effectively reducing switching losses. An experimental prototype with 42-55V input and 5 V/80 W output is built, demonstrating a peak efficiency of 95.1% .","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"388-396"},"PeriodicalIF":3.9,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11347510","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01DOI: 10.1109/OJPEL.2025.3647801
Ibrar Ali Wahla;Jongwoon Lee;Young-Ryul Yun;Muhammad Abrar Akram;In-Chul Hwang
This paper presents a fully-integrated all-digital low-dropout regulator (DLDO) for efficient fine-grained power delivery and management in system-on-chip (SoC) devices. The proposed DLDO is designed to drive both digital and analog load circuits, addressing their distinct requirements. An asynchronous coarse control ensures a fast load transient response to meet the dynamic demands of digital loads. In parallel, a fine-loop voltage stabilizer, equipped with dual-mode operation, enables ripple-free and precise voltage regulation essential for noise-sensitive analog loads. The dual-mode operation employs binary-shifting to quickly reach the target output voltage (${mathit{V}}_{mathit{OUT}}$), followed by unary-shifting for fine-tuned ${mathit{V}}_{mathit{OUT}}$ adjustment, thereby minimizing the output voltage ripples (${mathit{V}}_{mathit{RIPP}}$). Fabricated in a 65-nm CMOS process with an active area of 0.098 mm$^{2}$, the proposed DLDO operates with an input voltage (${mathit{V}}_{mathit{DD}}$) range of 0.6 V to 1.2 V and delivers a ${mathit{V}}_{mathit{OUT}}$ of 0.55 V to 1.15 V. Worst-case measurement results demonstrate the recovery time of $leq$ 30 ns for a 109 mV voltage droop when a (0 mA $rightarrow$ 25 mA) load current (${mathit{I}}_{mathit{LOAD}}$) is changed with an edge timing of 10 ns, achieving an overall figure-of-merit of 1.106 ns$^{2}$. The proposed DLDO achieves the worst-case ${mathit{V}}_{mathit{RIPP}}$ of $leq$ 2 mV while driving a minimum ${mathit{I}}_{mathit{LOAD}}$ of 0.5 mA.
本文提出了一种全集成的全数字低差稳压器（DLDO），用于在片上系统（SoC）器件中高效的细粒度功率传输和管理。所提出的DLDO设计用于驱动数字和模拟负载电路，以满足其不同的要求。异步粗控制确保了快速的负载瞬态响应，以满足数字负载的动态需求。同时，一个细回路电压稳定器，配备双模式操作，使无纹波和精确的电压调节必不可少的噪声敏感的模拟负载。双模操作采用二进制移位快速达到目标输出电压（${mathit{V}}_{mathit{OUT}}$），然后采用一元移位进行微调${mathit{V}}_{mathit{OUT}}$调整，从而最大限度地减少输出电压纹波（${mathit{V}}_{mathit{RIPP}}$）。该DLDO采用65纳米CMOS工艺制造，有效面积为0.098 mm $^{2}$，其输入电压（${mathit{V}}_{mathit{DD}}$）范围为0.6 V至1.2 V，输出电压${mathit{V}}_{mathit{OUT}}$为0.55 V至1.15 V。最坏情况下的测量结果表明，当（0 mA $rightarrow$ 25 mA）负载电流（${mathit{I}}_{mathit{LOAD}}$）以10 ns的边缘时间改变时，109 mV电压下降的恢复时间为$leq$ 30 ns，总体性能值为1.106 ns $^{2}$。提出的DLDO在驱动最小${mathit{I}}_{mathit{LOAD}}$为0.5 mA的情况下实现$leq$ 2 mV的最坏情况${mathit{V}}_{mathit{RIPP}}$。
{"title":"A Fast-Transient Digital LDO With Asynchronous Coarse and Dual-Mode Fine Regulation Loops","authors":"Ibrar Ali Wahla;Jongwoon Lee;Young-Ryul Yun;Muhammad Abrar Akram;In-Chul Hwang","doi":"10.1109/OJPEL.2025.3647801","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3647801","url":null,"abstract":"This paper presents a fully-integrated all-digital low-dropout regulator (DLDO) for efficient fine-grained power delivery and management in system-on-chip (SoC) devices. The proposed DLDO is designed to drive both digital and analog load circuits, addressing their distinct requirements. An asynchronous coarse control ensures a fast load transient response to meet the dynamic demands of digital loads. In parallel, a fine-loop voltage stabilizer, equipped with dual-mode operation, enables ripple-free and precise voltage regulation essential for noise-sensitive analog loads. The dual-mode operation employs binary-shifting to quickly reach the target output voltage (<inline-formula><tex-math>${mathit{V}}_{mathit{OUT}}$</tex-math></inline-formula>), followed by unary-shifting for fine-tuned <inline-formula><tex-math>${mathit{V}}_{mathit{OUT}}$</tex-math></inline-formula> adjustment, thereby minimizing the output voltage ripples (<inline-formula><tex-math>${mathit{V}}_{mathit{RIPP}}$</tex-math></inline-formula>). Fabricated in a 65-nm CMOS process with an active area of 0.098 mm<inline-formula><tex-math>$^{2}$</tex-math></inline-formula>, the proposed DLDO operates with an input voltage (<inline-formula><tex-math>${mathit{V}}_{mathit{DD}}$</tex-math></inline-formula>) range of 0.6 V to 1.2 V and delivers a <inline-formula><tex-math>${mathit{V}}_{mathit{OUT}}$</tex-math></inline-formula> of 0.55 V to 1.15 V. Worst-case measurement results demonstrate the recovery time of <inline-formula><tex-math>$leq$</tex-math></inline-formula> 30 ns for a 109 mV voltage droop when a (0 mA <inline-formula><tex-math>$rightarrow$</tex-math></inline-formula> 25 mA) load current (<inline-formula><tex-math>${mathit{I}}_{mathit{LOAD}}$</tex-math></inline-formula>) is changed with an edge timing of 10 ns, achieving an overall figure-of-merit of 1.106 ns<inline-formula><tex-math>$^{2}$</tex-math></inline-formula>. The proposed DLDO achieves the worst-case <inline-formula><tex-math>${mathit{V}}_{mathit{RIPP}}$</tex-math></inline-formula> of <inline-formula><tex-math>$leq$</tex-math></inline-formula> 2 mV while driving a minimum <inline-formula><tex-math>${mathit{I}}_{mathit{LOAD}}$</tex-math></inline-formula> of 0.5 mA.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"330-341"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11321315","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-30DOI: 10.1109/OJPEL.2025.3644589
Mohammad Shahjalal;Uvais Mustafa;Stoyan Stoyanov;Md. Rishad Ahmed
Magnetic component design is one of the key challenges for high-frequency DC-DC converters. Simple loss-based thermal analysis can be an alternative to achieving an effective electrothermal design for magnetics at the initial design stage, before the real prototype design, which can save cost and time. In this paper, a lumped thermal equivalent circuit (LTEC) model is developed to guide the thermal design of magnetic components. LTEC models are compared with finite element analysis (FEA) and experimental results. To capitalise on the amorphous core in designing high-current/high-frequency magnetic components, a physics-based analytical thermal model can be used to identify temperatures at specific nodes or points of interest. This lumped parameter-based method can be used for quick analysis and design optimisation, whereas FEA is better for identifying accurate temperature distribution and hot-spot temperatures and to guide the designers to achieve effective thermal design by adopting appropriate strategies such as potting or liquid cooling. This paper investigates two magnetic components in a high-frequency, interleaved DC-DC converter: one is the high current filter inductor, and the other is the interphase transformer (IPT). Both LTEC and FEA models are validated using experimental measurements from a 1.5 kW interleaved DC-DC converter prototype. The proposed LTEC results are comparable to both experimental and FEA results, and for the inductor, the average error is limited to 7.4% while for the IPT transformer average error is up to 5.7% .
{"title":"Lumped Thermal Model for Magnetic Components in an Interleaved DC–DC Converter","authors":"Mohammad Shahjalal;Uvais Mustafa;Stoyan Stoyanov;Md. Rishad Ahmed","doi":"10.1109/OJPEL.2025.3644589","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3644589","url":null,"abstract":"Magnetic component design is one of the key challenges for high-frequency DC-DC converters. Simple loss-based thermal analysis can be an alternative to achieving an effective electrothermal design for magnetics at the initial design stage, before the real prototype design, which can save cost and time. In this paper, a lumped thermal equivalent circuit (LTEC) model is developed to guide the thermal design of magnetic components. LTEC models are compared with finite element analysis (FEA) and experimental results. To capitalise on the amorphous core in designing high-current/high-frequency magnetic components, a physics-based analytical thermal model can be used to identify temperatures at specific nodes or points of interest. This lumped parameter-based method can be used for quick analysis and design optimisation, whereas FEA is better for identifying accurate temperature distribution and hot-spot temperatures and to guide the designers to achieve effective thermal design by adopting appropriate strategies such as potting or liquid cooling. This paper investigates two magnetic components in a high-frequency, interleaved DC-DC converter: one is the high current filter inductor, and the other is the interphase transformer (IPT). Both LTEC and FEA models are validated using experimental measurements from a 1.5 kW interleaved DC-DC converter prototype. The proposed LTEC results are comparable to both experimental and FEA results, and for the inductor, the average error is limited to 7.4% while for the IPT transformer average error is up to 5.7% .","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"226-238"},"PeriodicalIF":3.9,"publicationDate":"2025-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11318357","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-25DOI: 10.1109/OJPEL.2025.3648657
Arindam Sircar;Xiu Yao
The increase in operating voltage levels of power modules due to the adoption of wide bandgap semiconductor materials increases the risk of insulation breakdown and partial discharge. Modeling direct-bonded copper (DBC) and evaluating its electric field distribution is an important step for power module design. Finite Element Analysis (FEA) solvers, such as Ansys Maxwell and COMSOL Multiphysics, are popular tools to obtain accurate electric field information. However, these solvers are computationally expensive and time intensive. In this paper, a simple and accurate DBC model is developed. Schwarz-Christoffel Transformations are used to obtain an analytical formula to evaluate the electric field in the DBC model. The analytical models are verified against FEA models designed in Ansys Maxwell. The analytical method provides accurate electric field values while significantly reducing computation time.
{"title":"Maximum Electric Field Analysis in a Power Module Using Schwarz–Christoffel Transformation","authors":"Arindam Sircar;Xiu Yao","doi":"10.1109/OJPEL.2025.3648657","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3648657","url":null,"abstract":"The increase in operating voltage levels of power modules due to the adoption of wide bandgap semiconductor materials increases the risk of insulation breakdown and partial discharge. Modeling direct-bonded copper (DBC) and evaluating its electric field distribution is an important step for power module design. Finite Element Analysis (FEA) solvers, such as Ansys Maxwell and COMSOL Multiphysics, are popular tools to obtain accurate electric field information. However, these solvers are computationally expensive and time intensive. In this paper, a simple and accurate DBC model is developed. Schwarz-Christoffel Transformations are used to obtain an analytical formula to evaluate the electric field in the DBC model. The analytical models are verified against FEA models designed in Ansys Maxwell. The analytical method provides accurate electric field values while significantly reducing computation time.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"342-350"},"PeriodicalIF":3.9,"publicationDate":"2025-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11315122","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-24DOI: 10.1109/OJPEL.2025.3647775
Yann E. Bouvier;Yelena Fernandez-Zolotushchenko;Alba Rodriguez-Lorente;Joaquín Vaquero
The design of inductors is a complex and demanding task that often requires trial and error iterations, particularly in terms of size optimization. Typically, the design process starts with an initial core shape and size, followed by iterative “trial and error” adjustments to the core size to achieve optimal dimensions. The proposed method is purely analytical for the case of inductors non-limited by saturation (NLS) and for the cases that are limited by saturation (LS), typically requiring calculation iterations. The proposed method is intended as a scoping and scaling tool, so it can also be used as a scaling law for the energy density of inductors for comparing volumes for different specifications. The method includes the variability of input design parameters to account for the deviation between theoretical designs and actual implementations. Finally, a workflow is presented consisting of two iterations: the second iteration recalculates input parameters based on the initial core selection from the first pass, significantly reducing deviation from experimental results. The maximum deviation for the proposed method is improved from around $20%$–$35%$ on the first iteration to around $4%$–$20%$ for the second iteration.
{"title":"Area Product Equations for Inductor Energy Density Scaling Law With Input Design Parameter Variability","authors":"Yann E. Bouvier;Yelena Fernandez-Zolotushchenko;Alba Rodriguez-Lorente;Joaquín Vaquero","doi":"10.1109/OJPEL.2025.3647775","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3647775","url":null,"abstract":"The design of inductors is a complex and demanding task that often requires trial and error iterations, particularly in terms of size optimization. Typically, the design process starts with an initial core shape and size, followed by iterative “trial and error” adjustments to the core size to achieve optimal dimensions. The proposed method is purely analytical for the case of inductors non-limited by saturation (NLS) and for the cases that are limited by saturation (LS), typically requiring calculation iterations. The proposed method is intended as a scoping and scaling tool, so it can also be used as a scaling law for the energy density of inductors for comparing volumes for different specifications. The method includes the variability of input design parameters to account for the deviation between theoretical designs and actual implementations. Finally, a workflow is presented consisting of two iterations: the second iteration recalculates input parameters based on the initial core selection from the first pass, significantly reducing deviation from experimental results. The maximum deviation for the proposed method is improved from around <inline-formula><tex-math>$20%$</tex-math></inline-formula>–<inline-formula><tex-math>$35%$</tex-math></inline-formula> on the first iteration to around <inline-formula><tex-math>$4%$</tex-math></inline-formula>–<inline-formula><tex-math>$20%$</tex-math></inline-formula> for the second iteration.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"193-208"},"PeriodicalIF":3.9,"publicationDate":"2025-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11314746","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-23DOI: 10.1109/OJPEL.2025.3647112
Yimin Zhou;Zhiqiang Wang;Deao Shen;Chunyang Man;Xingshan Li;Guofei Hu;Xiaojie Shi
As materials and fabrication processes advance, the medium voltage (MV) silicon carbide (SiC) power semiconductors featuring exceptional electrothermal properties are emerging in high-power applications. Packaging technology, as the key bridge linking MV SiC power semiconductors to external systems, plays a vital role in fully harnessing their performance benefits. In this paper, a comprehensive overview of packaging technologies for MV SiC power modules is provided, focusing on critical aspects of package layout, parasitics, partial discharge, and cooling structure. Through the review, emerging challenges facing MV SiC packaging are detailed and salient distinctions from low voltage SiC packaging are highlighted. In addition, potential solutions are discussed, and insights into future technological trends are shared.
{"title":"Overview of Medium Voltage SiC Power Module Packaging Technologies: Layout, Insulation, and Cooling Structure","authors":"Yimin Zhou;Zhiqiang Wang;Deao Shen;Chunyang Man;Xingshan Li;Guofei Hu;Xiaojie Shi","doi":"10.1109/OJPEL.2025.3647112","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3647112","url":null,"abstract":"As materials and fabrication processes advance, the medium voltage (MV) silicon carbide (SiC) power semiconductors featuring exceptional electrothermal properties are emerging in high-power applications. Packaging technology, as the key bridge linking MV SiC power semiconductors to external systems, plays a vital role in fully harnessing their performance benefits. In this paper, a comprehensive overview of packaging technologies for MV SiC power modules is provided, focusing on critical aspects of package layout, parasitics, partial discharge, and cooling structure. Through the review, emerging challenges facing MV SiC packaging are detailed and salient distinctions from low voltage SiC packaging are highlighted. In addition, potential solutions are discussed, and insights into future technological trends are shared.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"249-266"},"PeriodicalIF":3.9,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11313521","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145982189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-23DOI: 10.1109/OJPEL.2025.3646981
Francesca Giardine;Sahana Krishnan;Yixuan Wu;Logan Horowitz;Robert C. N. Pilawa-Podgurski
This work proposes a variable switching frequency scheme for a flying capacitor multilevel (FCML) converter in dc-ac operation to better utilize the output inductor for its rated peak-to-peak current ripple and substantially reduce converter losses over the ac modulation cycle. The proposed technique holds the inductor current ripple constant by leveraging the duty-cycle-dependent inductor current ripple and varies the switching frequency to hold this current ripple constant at its rated design value. Furthermore, this technique can be leveraged to spread conducted electromagnetic interference peaks at both the input and output ports of the inverter. Practical lower switching limits are derived and taken into consideration in developing this approach, and experimental results validate the feasibility in a common microcontroller framework. Hardware results are provided for both 6-level and 8-level FCML inverters and showcase loss reductions and improved electromagnetic interference performance.
{"title":"A Variable Frequency Technique for EMI and Efficiency Improvements in High-Level Count Flying Capacitor Multilevel Converters","authors":"Francesca Giardine;Sahana Krishnan;Yixuan Wu;Logan Horowitz;Robert C. N. Pilawa-Podgurski","doi":"10.1109/OJPEL.2025.3646981","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3646981","url":null,"abstract":"This work proposes a variable switching frequency scheme for a flying capacitor multilevel (FCML) converter in dc-ac operation to better utilize the output inductor for its rated peak-to-peak current ripple and substantially reduce converter losses over the ac modulation cycle. The proposed technique holds the inductor current ripple constant by leveraging the duty-cycle-dependent inductor current ripple and varies the switching frequency to hold this current ripple constant at its rated design value. Furthermore, this technique can be leveraged to spread conducted electromagnetic interference peaks at both the input and output ports of the inverter. Practical lower switching limits are derived and taken into consideration in developing this approach, and experimental results validate the feasibility in a common microcontroller framework. Hardware results are provided for both 6-level and 8-level FCML inverters and showcase loss reductions and improved electromagnetic interference performance.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"267-280"},"PeriodicalIF":3.9,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11313473","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145982262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-19DOI: 10.1109/OJPEL.2025.3646456
Jack Forrester;Jonathan N. Davidson;Martin P. Foster
Cyclic-mode analysis is used to analyse the inductorless step-up piezoelectric-resonator (SUPR) converter. The operation of the converter is decomposed into six operating modes and a non-linear state-variable model is derived. The state-variable model is then transformed into a piecewise linear model based on the operating modes, which can then be subsequently solved in parallel with the optimum operating mode durations using Newton's method. For a set of circuit and piezoelectric resonator (PR) parameters, the proposed model allows various voltages and currents to be estimated. The accuracy of this model is verified against experimental and Simulink results, as well as being compared to state-of-the-art models. The proposed model shows improved accuracy compared to previous models, particularly for low-Q PRs.
{"title":"Inductorless Step-Up Piezoelectric Resonator (SUPR) Converter: A Cyclic-Mode Analysis","authors":"Jack Forrester;Jonathan N. Davidson;Martin P. Foster","doi":"10.1109/OJPEL.2025.3646456","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3646456","url":null,"abstract":"Cyclic-mode analysis is used to analyse the inductorless step-up piezoelectric-resonator (SUPR) converter. The operation of the converter is decomposed into six operating modes and a non-linear state-variable model is derived. The state-variable model is then transformed into a piecewise linear model based on the operating modes, which can then be subsequently solved in parallel with the optimum operating mode durations using Newton's method. For a set of circuit and piezoelectric resonator (PR) parameters, the proposed model allows various voltages and currents to be estimated. The accuracy of this model is verified against experimental and Simulink results, as well as being compared to state-of-the-art models. The proposed model shows improved accuracy compared to previous models, particularly for low-Q PRs.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"239-248"},"PeriodicalIF":3.9,"publicationDate":"2025-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11304707","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145982195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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