Pub Date : 2025-02-18DOI: 10.1109/OJPEL.2025.3543247
S. Foti;C. Nevoloso;H. H. Khan;A. O. Di Tommaso;A. Testa;R. Miceli
This paper proposes a simple mixed-carrier-based PWM strategy driven through a hysteresis control to address the issues related to voltage imbalances and low-frequency oscillation in the DC-link capacitors voltage. The goal of this approach is to avoid extra power losses, power quality issues and reduced lifespan of capacitors by exploiting the features of conventional dual-carrier PWM strategies. This technique offers a remarkably low computational burden, outstanding performance in terms of power quality and losses, and it does not require additional power circuits. The proposed approach is first introduced theoretically, then its performance is exhaustively assessed through simulations and experimental tests by demonstrating a significant reduction of capacitor sizing. Additionally, an experimental performance comparison analysis is performed with a conventional three-level PWM strategy. Finally, to prove its merits with respect to other carrier-based PWM strategies proposed in the literature, a comparison in terms of current and voltage transducers, control algorithm complexity, computational cost and total harmonic distortion is provided.
{"title":"A Simple Carrier-Based Neutral Point Voltage Control Strategy for NPC Three-Level Inverters","authors":"S. Foti;C. Nevoloso;H. H. Khan;A. O. Di Tommaso;A. Testa;R. Miceli","doi":"10.1109/OJPEL.2025.3543247","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3543247","url":null,"abstract":"This paper proposes a simple mixed-carrier-based PWM strategy driven through a hysteresis control to address the issues related to voltage imbalances and low-frequency oscillation in the DC-link capacitors voltage. The goal of this approach is to avoid extra power losses, power quality issues and reduced lifespan of capacitors by exploiting the features of conventional dual-carrier PWM strategies. This technique offers a remarkably low computational burden, outstanding performance in terms of power quality and losses, and it does not require additional power circuits. The proposed approach is first introduced theoretically, then its performance is exhaustively assessed through simulations and experimental tests by demonstrating a significant reduction of capacitor sizing. Additionally, an experimental performance comparison analysis is performed with a conventional three-level PWM strategy. Finally, to prove its merits with respect to other carrier-based PWM strategies proposed in the literature, a comparison in terms of current and voltage transducers, control algorithm complexity, computational cost and total harmonic distortion is provided.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"416-431"},"PeriodicalIF":5.0,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10891821","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143563976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-13DOI: 10.1109/OJPEL.2025.3541836
Nícolas Baschera;Marco Di Benedetto;Alessandro Lidozzi;Luca Solero;Petar J. Grbović
The traditional machine test benches are known for their inflexibility, safety concerns, weight, and cost. The adoption of Power Hardware-in-the-Loop (PHIL) has been appearing as an enhanced technique to test and validate control algorithms and hardware of Variable Speed Drives (VSDs) for electrical machines. This paper presents the use of the PHIL for the emulation of a Permanent Magnet Synchronous Machine (PMSM) using an LCL coupling network with voltage control. The principle of operation, modeling and control structures are presented in detail. The presented strategy allows the Electrical Machine Emulator (EME) to decouple the low fundamental frequency of the machine from the high frequency (current ripple) of the Device Under Test (DUT) during its operation. The use of different inductances for the reproduction of a machine with a fixed synchronous inductance is addressed in detail, besides the consequences on the current ripple. The theoretical work is supported and validated through experimental tests using an FPGA-Based Real Time Simulator and dedicated control boards (PED-Board).
{"title":"Decoupling Current Ripple in PHIL PMSM Emulation Using LCL Filter: A Fundamental Frequency Analysis","authors":"Nícolas Baschera;Marco Di Benedetto;Alessandro Lidozzi;Luca Solero;Petar J. Grbović","doi":"10.1109/OJPEL.2025.3541836","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3541836","url":null,"abstract":"The traditional machine test benches are known for their inflexibility, safety concerns, weight, and cost. The adoption of Power Hardware-in-the-Loop (PHIL) has been appearing as an enhanced technique to test and validate control algorithms and hardware of Variable Speed Drives (VSDs) for electrical machines. This paper presents the use of the PHIL for the emulation of a Permanent Magnet Synchronous Machine (PMSM) using an LCL coupling network with voltage control. The principle of operation, modeling and control structures are presented in detail. The presented strategy allows the Electrical Machine Emulator (EME) to decouple the low fundamental frequency of the machine from the high frequency (current ripple) of the Device Under Test (DUT) during its operation. The use of different inductances for the reproduction of a machine with a fixed synchronous inductance is addressed in detail, besides the consequences on the current ripple. The theoretical work is supported and validated through experimental tests using an FPGA-Based Real Time Simulator and dedicated control boards (PED-Board).","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"401-415"},"PeriodicalIF":5.0,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10884891","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143535562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-10DOI: 10.1109/OJPEL.2025.3540347
Debora P. Damasceno;Paolo Sbabo;Mateus P. Dias;José C. U. Peña;Joel Filipe Guerreiro;Paolo Mattavelli;José Antenor Pomilio
This article examines high-frequency disturbances in interconnected converters within dc microgrids, focusing on the effects of electromagnetic interference (EMI) filters and long interconnection cables. Understanding these phenomena is essential for systems with multiple power converters as it facilitates the identification and mitigation of voltage and current oscillations. The study investigates the beating effect in dc microgrids, providing an analytical derivation of the oscillation amplitudes at the beat frequency. It also explores how interactions between long cables inductive impedance and EMI filter capacitors can influence the system performance, distinguishing it from previous works. The study examines a dc microgrid consisting of two connected cascaded buck converters. Two scenarios are analyzed: one considers no filters between the two converters, while the other includes a low-pass filter (LPF), an EMI filter, and a cable feeder between them. The proposed theoretical models are validated using a 2 kW experimental prototype comprising two interconnected buck converters. In addition, the paper presents various strategies to mitigate the beating effect in dc microgrids, discussing their effectiveness and the associated implementation challenges.
{"title":"DC Bus Voltage High-Frequency Disturbances Analysis for DC Microgrids With Long Connections","authors":"Debora P. Damasceno;Paolo Sbabo;Mateus P. Dias;José C. U. Peña;Joel Filipe Guerreiro;Paolo Mattavelli;José Antenor Pomilio","doi":"10.1109/OJPEL.2025.3540347","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3540347","url":null,"abstract":"This article examines high-frequency disturbances in interconnected converters within dc microgrids, focusing on the effects of electromagnetic interference (EMI) filters and long interconnection cables. Understanding these phenomena is essential for systems with multiple power converters as it facilitates the identification and mitigation of voltage and current oscillations. The study investigates the beating effect in dc microgrids, providing an analytical derivation of the oscillation amplitudes at the beat frequency. It also explores how interactions between long cables inductive impedance and EMI filter capacitors can influence the system performance, distinguishing it from previous works. The study examines a dc microgrid consisting of two connected cascaded buck converters. Two scenarios are analyzed: one considers no filters between the two converters, while the other includes a low-pass filter (LPF), an EMI filter, and a cable feeder between them. The proposed theoretical models are validated using a 2 kW experimental prototype comprising two interconnected buck converters. In addition, the paper presents various strategies to mitigate the beating effect in dc microgrids, discussing their effectiveness and the associated implementation challenges.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"371-382"},"PeriodicalIF":5.0,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10878503","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143480795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-10DOI: 10.1109/OJPEL.2025.3540079
Shaokang Luan;Hongbo Zhao
Parasitic capacitances are important in magnetic components, especially for the high-frequency power electronic converters enabled by wide-bandgap semiconductors. For the clearer and more structural understanding of parasitic capacitance in magnetic components, this paper provides a comprehensive compendium of parasitic capacitance including the definition, quantification, and modelling. Different types of parasitic capacitances based on intrinsic properties are defined with corresponding frequency ranges of interest. Both frequency-domain and time-domain measurement methods are introduced for more accurate and convincing quantification. As for the physical mechanism and modelling of parasitic capacitances, energy-based, transmission-line, and behaviour-based approaches are discussed. In the end, the challenges and perspectives are provided for further inspirations.
{"title":"Parasitic Capacitances in Magnetic Components: Overview and Perspectives","authors":"Shaokang Luan;Hongbo Zhao","doi":"10.1109/OJPEL.2025.3540079","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3540079","url":null,"abstract":"Parasitic capacitances are important in magnetic components, especially for the high-frequency power electronic converters enabled by wide-bandgap semiconductors. For the clearer and more structural understanding of parasitic capacitance in magnetic components, this paper provides a comprehensive compendium of parasitic capacitance including the definition, quantification, and modelling. Different types of parasitic capacitances based on intrinsic properties are defined with corresponding frequency ranges of interest. Both frequency-domain and time-domain measurement methods are introduced for more accurate and convincing quantification. As for the physical mechanism and modelling of parasitic capacitances, energy-based, transmission-line, and behaviour-based approaches are discussed. In the end, the challenges and perspectives are provided for further inspirations.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"383-400"},"PeriodicalIF":5.0,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10878814","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-07DOI: 10.1109/OJPEL.2025.3538881
Shinan Wang;Xizheng Guo;Yueqing Chen;Zonghui Sun;Xiaojie You
This article proposes a silicon carbide (SiC) MOSFET transient model on the field programmable gate array (FPGA), which is suitable for the real-time simulation (RTS) of power electronic converters. The model describes the transient process with state equations, which is segmented by the time-scale, and achieves accurate simulation results with small time-step. Compared with the existing research that simplifies SiC MOSFET model in the RTS implementation process, the proposed modeling method not only considers the hard-switching process caused by insufficient deadtime, and the special switching mode that the channel turn-off precedes the antiparallel diode turn-on in opposite device, but also fits the nonlinear characteristics of the SiC MOSFET through look-up tables (LUTs). In addtion, the parallel solution structure of the FPGA-based RTS model is completed through hardware optimization design scheme. Combined with circuit decoupling technology, the model can be solved by the Backward Euler (BE) discretization method with time-step of 10 ns. Subsequently, the effectiveness and accuracy of the modeling method are validated by the simulation and hardware experiments.
{"title":"An Accurate SiC MOSFET Transient Modeling Method for the FPGA-Based Real-Time Simulation of Power Electronic Converters","authors":"Shinan Wang;Xizheng Guo;Yueqing Chen;Zonghui Sun;Xiaojie You","doi":"10.1109/OJPEL.2025.3538881","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3538881","url":null,"abstract":"This article proposes a silicon carbide (SiC) MOSFET transient model on the field programmable gate array (FPGA), which is suitable for the real-time simulation (RTS) of power electronic converters. The model describes the transient process with state equations, which is segmented by the time-scale, and achieves accurate simulation results with small time-step. Compared with the existing research that simplifies SiC MOSFET model in the RTS implementation process, the proposed modeling method not only considers the hard-switching process caused by insufficient deadtime, and the special switching mode that the channel turn-off precedes the antiparallel diode turn-on in opposite device, but also fits the nonlinear characteristics of the SiC MOSFET through look-up tables (LUTs). In addtion, the parallel solution structure of the FPGA-based RTS model is completed through hardware optimization design scheme. Combined with circuit decoupling technology, the model can be solved by the Backward Euler (BE) discretization method with time-step of 10 ns. Subsequently, the effectiveness and accuracy of the modeling method are validated by the simulation and hardware experiments.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"344-353"},"PeriodicalIF":5.0,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10877787","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143480799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three-level diode-neutral-point-clamped (DNPC)-LLC resonant converter is usually utilized for high input voltage applications, whereas its output voltage is regulated using three-level (3L) modulation method. However, 3L modulation makes it difficult to address the requirement of a wide output voltage range. Therefore, this paper presents a hybrid modulation method for the DNPC-LLC converter, incorporating the traditional 3L modulation and a proposed two-level (2L) modulation, which allows lower output voltages, reduces the switching frequency and the number of switching operations of the primary-side switches. Furthermore, the operating principles and voltage gains of both modulation methods are analyzed. Finally, a 3.7 kW SiC-based DNPC-LLC converter with synchronous rectification at an 800 V input is implemented. The output voltage ranges from 20 V to 450 V, and smooth transitions between different modulation modes are verified. The proposed converter achieves a maximum efficiency of 97.3% at an output of 360 V and 10.3 A. Furthermore, compared to the 3L method, the 2L method improves efficiency by at least 0.5% when the output voltage is below 200 V. Additionally, the voltage balance between two series dc-link capacitors is fulfilled after applying voltage balancing control.
三电平二极管中性点钳位（DNPC）-LLC 谐振转换器通常用于高输入电压应用，而其输出电压则采用三电平（3L）调制方法进行调节。然而，3L 调制很难满足宽输出电压范围的要求。因此，本文为 DNPC-LLC 转换器提出了一种混合调制方法，它结合了传统的 3L 调制和建议的两电平 (2L) 调制，可实现更低的输出电压，降低开关频率和一次侧开关操作次数。此外，还分析了两种调制方法的工作原理和电压增益。最后，实现了一个基于碳化硅的 3.7 千瓦 DNPC-LLC 转换器，在 800 V 输入电压下进行同步整流。输出电压范围为 20 V 至 450 V，并验证了不同调制模式之间的平滑转换。此外，与 3L 方法相比，当输出电压低于 200 V 时，2L 方法的效率至少提高了 0.5%。此外，在应用电压平衡控制后，两个串联直流链路电容器之间的电压平衡得以实现。
{"title":"Three-Level DNPC-LLC Converter With Hybrid Modulation Method for Wide Output Voltage Applications","authors":"Ming-Shi Huang;Jhih-Cheng Hu;Shih-Gang Chen;Wei-Hsiang Hsu;Chun-Wei Huang","doi":"10.1109/OJPEL.2025.3539667","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3539667","url":null,"abstract":"Three-level diode-neutral-point-clamped (DNPC)-LLC resonant converter is usually utilized for high input voltage applications, whereas its output voltage is regulated using three-level (3L) modulation method. However, 3L modulation makes it difficult to address the requirement of a wide output voltage range. Therefore, this paper presents a hybrid modulation method for the DNPC-LLC converter, incorporating the traditional 3L modulation and a proposed two-level (2L) modulation, which allows lower output voltages, reduces the switching frequency and the number of switching operations of the primary-side switches. Furthermore, the operating principles and voltage gains of both modulation methods are analyzed. Finally, a 3.7 kW SiC-based DNPC-LLC converter with synchronous rectification at an 800 V input is implemented. The output voltage ranges from 20 V to 450 V, and smooth transitions between different modulation modes are verified. The proposed converter achieves a maximum efficiency of 97.3% at an output of 360 V and 10.3 A. Furthermore, compared to the 3L method, the 2L method improves efficiency by at least 0.5% when the output voltage is below 200 V. Additionally, the voltage balance between two series dc-link capacitors is fulfilled after applying voltage balancing control.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"354-370"},"PeriodicalIF":5.0,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10878305","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143480802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a robust control approach for non-isolated Modular Multiport Converters (MMPC) capable of integrating multiple energy sources and loads. The objective of this robust control approach is to mitigate cross-coupling challenges inherent in MIMO systems and effectively manage the parametric uncertainties associated with the converter as well as input and output disturbances. To achieve this objective, the paper begins with deriving the general nonlinear dynamic equations of an n-level step-up multi-port DC/DC converter (${MPDC}_{nL}^{SU}$). Subsequently, for a case study involving a 3-level step-up multi-port DC/DC converter (${MPDC}_{3L}^{SU}$) the equations are linearized to obtain the state-space model. Following the derivation of the converter model, a controller comprising two control loops is designed. The outer loop, responsible for regulating the voltage of output ports, is synthesized through a robust μ-optimal method using the ${D} - mathcal{G} - mathcal{K}$ iterative procedure, while the inner loop, responsible for regulating the current sharing among the parallel modules and generating PWM signals, is stabilized via multiple PI controllers. Finally, hardware-in-the-loop (HIL) test results derived from OPAL-RT 4610, and experimental results from a prototype are used to validate this control approach. The proposed decoupled mixed ${mu }$ synthesis method ensures robust performance and stability and results in a less conservative controller design for the ${MPDC}_{3L}^{SU}$.
{"title":"Robust Control of Modular Multiport DC–DC Converter","authors":"Shahriar Farajdadian;Amin Hajizadeh;Mohsen Soltani;Pavol Bauer;Hani Vahedi","doi":"10.1109/OJPEL.2025.3538992","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3538992","url":null,"abstract":"This paper presents a robust control approach for non-isolated Modular Multiport Converters (MMPC) capable of integrating multiple energy sources and loads. The objective of this robust control approach is to mitigate cross-coupling challenges inherent in MIMO systems and effectively manage the parametric uncertainties associated with the converter as well as input and output disturbances. To achieve this objective, the paper begins with deriving the general nonlinear dynamic equations of an n-level step-up multi-port DC/DC converter (<inline-formula><tex-math>${MPDC}_{nL}^{SU}$</tex-math></inline-formula>). Subsequently, for a case study involving a 3-level step-up multi-port DC/DC converter (<inline-formula><tex-math>${MPDC}_{3L}^{SU}$</tex-math></inline-formula>) the equations are linearized to obtain the state-space model. Following the derivation of the converter model, a controller comprising two control loops is designed. The outer loop, responsible for regulating the voltage of output ports, is synthesized through a robust μ-optimal method using the <inline-formula><tex-math>${D} - mathcal{G} - mathcal{K}$</tex-math></inline-formula> iterative procedure, while the inner loop, responsible for regulating the current sharing among the parallel modules and generating PWM signals, is stabilized via multiple PI controllers. Finally, hardware-in-the-loop (HIL) test results derived from OPAL-RT 4610, and experimental results from a prototype are used to validate this control approach. The proposed decoupled mixed <inline-formula><tex-math>${mu }$</tex-math></inline-formula> synthesis method ensures robust performance and stability and results in a less conservative controller design for the <inline-formula><tex-math>${MPDC}_{3L}^{SU}$</tex-math></inline-formula>.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"300-313"},"PeriodicalIF":5.0,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10878119","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-03DOI: 10.1109/OJPEL.2025.3537939
Amr Ahmed A. Radwan;Mahmoud Awad Elshenawy;Yasser Abdel-Rady I. Mohamed;Ehab F. El-Saadany
This paper presents a grid-forming (GFM) current-source (CSC)-based full-scale wind energy conversion system with detailed small-signal modeling, dynamic analysis, and systematic control design approach. The system comprises 1) a machine-side vector-controlled CSC to regulate the power extracted from the permanent-magnet synchronous generator-based wind turbine, where a practical two-mass drivetrain model is adopted, and 2) a grid-side CSC controlled by a GFM scheme to support the grid and regulate the dc-link current to maintain a stable delivery of the extracted wind power. A detailed small-signal state-space model of the overall CSC-based system is developed to investigate the system's stability under different practical parameters, such as wind power reserve, control parameter, and short-circuit ratio variation. The equivalent dc-side impedances of the grid and machine-side CSCs are also developed and used to characterize the dc-link stability using the Nyquist stability criterion. A systematic design approach for the control parameters is presented. Nonlinear-model time-domain simulations are presented to verify the analytical results and assess the performance under various operating conditions, such as grid disturbances, faults, and parameter uncertainty. This study shows that the GFM CSC system provides stable operation under weak and very weak grid conditions and robust performance under fault conditions compared to a similar GFM voltage-source converter system.
{"title":"Grid-Forming Current-Source Converter for a Full-Scale Wind Energy Conversion System","authors":"Amr Ahmed A. Radwan;Mahmoud Awad Elshenawy;Yasser Abdel-Rady I. Mohamed;Ehab F. El-Saadany","doi":"10.1109/OJPEL.2025.3537939","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3537939","url":null,"abstract":"This paper presents a grid-forming (GFM) current-source (CSC)-based full-scale wind energy conversion system with detailed small-signal modeling, dynamic analysis, and systematic control design approach. The system comprises 1) a machine-side vector-controlled CSC to regulate the power extracted from the permanent-magnet synchronous generator-based wind turbine, where a practical two-mass drivetrain model is adopted, and 2) a grid-side CSC controlled by a GFM scheme to support the grid and regulate the dc-link current to maintain a stable delivery of the extracted wind power. A detailed small-signal state-space model of the overall CSC-based system is developed to investigate the system's stability under different practical parameters, such as wind power reserve, control parameter, and short-circuit ratio variation. The equivalent dc-side impedances of the grid and machine-side CSCs are also developed and used to characterize the dc-link stability using the Nyquist stability criterion. A systematic design approach for the control parameters is presented. Nonlinear-model time-domain simulations are presented to verify the analytical results and assess the performance under various operating conditions, such as grid disturbances, faults, and parameter uncertainty. This study shows that the GFM CSC system provides stable operation under weak and very weak grid conditions and robust performance under fault conditions compared to a similar GFM voltage-source converter system.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"327-343"},"PeriodicalIF":5.0,"publicationDate":"2025-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10870106","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-28DOI: 10.1109/OJPEL.2025.3535761
Saman Shoorabi Sani
This article proposes a new interface circuit for Piezoelectric Energy Harvesters (PEHs), which improves the startup issue of the Synchronized Switch Harvesting on Inductor (SSHI) technique in variable amplitude vibration environments. In the proposed Increased Input Range Synchronized Switch Harvesting on Inductor (IIR-SSHI), once the SSHI scheme stops operating because of the change in the excitation amplitude, a low-power peak detector is activated to accumulate the charge of the parasitic capacitance of the PEH by successive bias-flipping actions, without requiring any external energy investment, i.e., energy kick start. Therefore, the proposed circuit can autonomously maintain the energy extraction procedure active at the highest performance of energy extraction, i.e., FoMMOPIR, when the excitation amplitude is reduced considerably. The proposed circuit is simulated and verified using a 0.18-μm CMOS standard technology, ensuring energy extraction performance and robustness. Based on the post-layout simulation results, the proposed circuit can extract energy from PEH significantly for a minimum input excitation amplitude of only 800 mV. The maximum output power improvement relative to the Standard Energy Harvesting (SEH) and standard SSHI circuits is 5.5 and 2.75 in decreased input amplitude scenarios, respectively.
{"title":"An Efficient Autonomous Increased Input Range SSHI Interface for a Variable Amplitude Vibration","authors":"Saman Shoorabi Sani","doi":"10.1109/OJPEL.2025.3535761","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3535761","url":null,"abstract":"This article proposes a new interface circuit for Piezoelectric Energy Harvesters (PEHs), which improves the startup issue of the Synchronized Switch Harvesting on Inductor (SSHI) technique in variable amplitude vibration environments. In the proposed Increased Input Range Synchronized Switch Harvesting on Inductor (IIR-SSHI), once the SSHI scheme stops operating because of the change in the excitation amplitude, a low-power peak detector is activated to accumulate the charge of the parasitic capacitance of the PEH by successive bias-flipping actions, without requiring any external energy investment, i.e., energy kick start. Therefore, the proposed circuit can autonomously maintain the energy extraction procedure active at the highest performance of energy extraction, i.e., FoM<sub>MOPIR</sub>, when the excitation amplitude is reduced considerably. The proposed circuit is simulated and verified using a 0.18-μm CMOS standard technology, ensuring energy extraction performance and robustness. Based on the post-layout simulation results, the proposed circuit can extract energy from PEH significantly for a minimum input excitation amplitude of only 800 mV. The maximum output power improvement relative to the Standard Energy Harvesting (SEH) and standard SSHI circuits is 5.5 and 2.75 in decreased input amplitude scenarios, respectively.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"314-326"},"PeriodicalIF":5.0,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10856550","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Misalignment tolerance and receiver positioning are critical in designing wireless charging systems for electric vehicles. This study presents a magnetic field editable wireless power transfer (MFE-WPT) system equipped with the orthogonally-stacked double-D (DD2) magnetic coupler and a new control strategy, equivalently modifying the magnetic field distribution to tolerate misalignments without physically adjusting the receiver position. In this paper, the detailed analysis of circuit modeling, transfer characteristics, magnetic field distribution and position recognition strategy of the MEF-WPT system are given. Besides, an experimental prototype with the output power of 2.3 kW and the system efficiency of 87.99% has been built and four different receiver positions are selected to validate the effectiveness of the proposed system. By comparing with the traditional DD coil based WPT system, the measured results of the proposed system can maximumly improve the output power and system efficiency up to 2667.39% and 62.29%, when the receiver misalignment happens in the 200 × 200 mm charging plane.
{"title":"Magnetic-Field-Editable Wireless Power Transfer System With DD2 Magnetic Couplers for Position Detection and Misalignment Tolerance","authors":"Xuxing Duan;Wei Han;Youhao Hu;Hanlei Tian;Jinliang Huang;Zhen Zhang","doi":"10.1109/OJPEL.2025.3534245","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3534245","url":null,"abstract":"Misalignment tolerance and receiver positioning are critical in designing wireless charging systems for electric vehicles. This study presents a magnetic field editable wireless power transfer (MFE-WPT) system equipped with the orthogonally-stacked double-D (DD<sup>2</sup>) magnetic coupler and a new control strategy, equivalently modifying the magnetic field distribution to tolerate misalignments without physically adjusting the receiver position. In this paper, the detailed analysis of circuit modeling, transfer characteristics, magnetic field distribution and position recognition strategy of the MEF-WPT system are given. Besides, an experimental prototype with the output power of 2.3 kW and the system efficiency of 87.99% has been built and four different receiver positions are selected to validate the effectiveness of the proposed system. By comparing with the traditional DD coil based WPT system, the measured results of the proposed system can maximumly improve the output power and system efficiency up to 2667.39% and 62.29%, when the receiver misalignment happens in the 200 × 200 mm charging plane.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"266-276"},"PeriodicalIF":5.0,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10854645","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143361029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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