{"title":"针对低功耗应用的带 ADL 缓冲器的全局 RC 互连器件","authors":"Himani Bhardwaj, Shruti Jain, Harsh Sohal","doi":"10.2174/0118764029298466240508091306","DOIUrl":null,"url":null,"abstract":"\n\nInterconnects are an essential requirement for any circuit completion. They\nare utilised to connect two or more blocks, yet when creating a circuit, certain problems have been\nobserved. Scaling back technology is one such problem.\n\n\n\nWith technology scaled down their aspects change which can straightforwardly affect the\ncircuit boundaries. Because of this, the time constant and power consumption in the interconnect circuits\nhas increased. Certain wire (RC) models and techniques have previously been characterized to\ncontrol these performance parameters however in this paper, authors have proposed a new interconnect\nstructure with a buffer insertion technique using adiabatic dynamic logic (ADL).\n\n\n\nTo optimise power, a Schmitt trigger is inserted as a buffer between lengthy interconnect\ncircuits utilising an energy-recovery mechanism. The TSPICE tool is used to model and simulate the\nentire circuit.\n\n\n\nThe suggested model's performance is compared to that of other cutting-edge methods.\n\n\n\nThe complete circuits are modelled and simulated using the SPICE tool. A performance comparison is done between the existing model and the proposed model.\n","PeriodicalId":18543,"journal":{"name":"Micro and Nanosystems","volume":" 18","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Global RC Interconnects with ADL Buffers for Low-Power Applications\",\"authors\":\"Himani Bhardwaj, Shruti Jain, Harsh Sohal\",\"doi\":\"10.2174/0118764029298466240508091306\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\\n\\nInterconnects are an essential requirement for any circuit completion. They\\nare utilised to connect two or more blocks, yet when creating a circuit, certain problems have been\\nobserved. Scaling back technology is one such problem.\\n\\n\\n\\nWith technology scaled down their aspects change which can straightforwardly affect the\\ncircuit boundaries. Because of this, the time constant and power consumption in the interconnect circuits\\nhas increased. Certain wire (RC) models and techniques have previously been characterized to\\ncontrol these performance parameters however in this paper, authors have proposed a new interconnect\\nstructure with a buffer insertion technique using adiabatic dynamic logic (ADL).\\n\\n\\n\\nTo optimise power, a Schmitt trigger is inserted as a buffer between lengthy interconnect\\ncircuits utilising an energy-recovery mechanism. The TSPICE tool is used to model and simulate the\\nentire circuit.\\n\\n\\n\\nThe suggested model's performance is compared to that of other cutting-edge methods.\\n\\n\\n\\nThe complete circuits are modelled and simulated using the SPICE tool. A performance comparison is done between the existing model and the proposed model.\\n\",\"PeriodicalId\":18543,\"journal\":{\"name\":\"Micro and Nanosystems\",\"volume\":\" 18\",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-05-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Micro and Nanosystems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.2174/0118764029298466240508091306\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"Engineering\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Micro and Nanosystems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.2174/0118764029298466240508091306","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"Engineering","Score":null,"Total":0}
Global RC Interconnects with ADL Buffers for Low-Power Applications
Interconnects are an essential requirement for any circuit completion. They
are utilised to connect two or more blocks, yet when creating a circuit, certain problems have been
observed. Scaling back technology is one such problem.
With technology scaled down their aspects change which can straightforwardly affect the
circuit boundaries. Because of this, the time constant and power consumption in the interconnect circuits
has increased. Certain wire (RC) models and techniques have previously been characterized to
control these performance parameters however in this paper, authors have proposed a new interconnect
structure with a buffer insertion technique using adiabatic dynamic logic (ADL).
To optimise power, a Schmitt trigger is inserted as a buffer between lengthy interconnect
circuits utilising an energy-recovery mechanism. The TSPICE tool is used to model and simulate the
entire circuit.
The suggested model's performance is compared to that of other cutting-edge methods.
The complete circuits are modelled and simulated using the SPICE tool. A performance comparison is done between the existing model and the proposed model.