规模 CMOS 器件高κ金属栅极堆栈点缺陷的 Ab Initio 材料建模:变异性与有效功函数工程设计

IF 2.2 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Journal of Electronic Materials Pub Date : 2024-08-07 DOI:10.1007/s11664-024-11347-8
Rajan Kumar Pandey
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摘要

硅(Si)及其氧化物(SiO2)一直是推动半导体行业发展的主力军。将近十五年前,英特尔公司在 45 纳米技术中引入了高κ金属栅极(HKMG),IBM 公司在基于 32 纳米的互补金属氧化物半导体(CMOS)技术中引入了高κ金属栅极(HKMG),其中氧化铪(HfO2)和氮化钛(TiN)分别作为首选的高κ电介质和功函数金属被用于栅极堆栈中。这些 5 纳米以下甚至更高的按比例 CMOS 器件的性能取决于对块体材料和界面材料在化学成分、原子种类性质和缺陷方面的精确控制。栅极氧化物及其界面上的缺陷会影响阈值电压偏移和迁移率下降。通过基于密度泛函理论的第一原理建模,我们讨论了设计有效功函数 (EWF) 的方法。我们还讨论了有效功函数的可变性,以及由于 HKMG 堆栈中存在氧点缺陷而产生的可靠性问题。我们指出了通过材料创新、点缺陷和界面偶极子工程来实现有效功函数工程的可能性,以便在 5 纳米以下技术中实现大规模 CMOS 器件所需的阈值电压 (VT)。
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Ab Initio Materials Modeling of Point Defects in a High-κ Metal Gate Stack of Scaled CMOS Devices: Variability Versus Engineering the Effective Work Function

Silicon (Si) and its oxide (SiO2) have been the workhorse of the scaling-driven semiconductor industry. Almost a decade and a half ago, the high-κ metal gate (HKMG) was introduced by Intel for 45-nm technology and by IBM for 32-nm-based complementary metal–oxide–semiconductor (CMOS) technology, wherein hafnium oxide (HfO2) and titanium nitride (TiN) were used in the gate stack as the preferred high-κ dielectric and work function metal, respectively. The performance of these scaled CMOS devices at sub-5 nm and beyond relies on accurate control of materials in the bulk and at the interfaces in terms of chemical composition, nature of atomic species, and defects. The defects in gate oxides and at their interfaces influence the threshold voltage shift and mobility degradation. Employing first-principles modeling based on density functional theory, we discuss ways to engineer the effective work function (EWF). We also discuss the variability in the EWF and the reliability issues due to the presence of oxygen point defects in the HKMG stack. We point out the possibilities for EWF engineering through material innovation, point defects, and interface dipole engineering, in order to achieve the required threshold voltage (VT) of aggressively scaled CMOS devices at sub-5-nm technologies.

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来源期刊
Journal of Electronic Materials
Journal of Electronic Materials 工程技术-材料科学:综合
CiteScore
4.10
自引率
4.80%
发文量
693
审稿时长
3.8 months
期刊介绍: The Journal of Electronic Materials (JEM) reports monthly on the science and technology of electronic materials, while examining new applications for semiconductors, magnetic alloys, dielectrics, nanoscale materials, and photonic materials. The journal welcomes articles on methods for preparing and evaluating the chemical, physical, electronic, and optical properties of these materials. Specific areas of interest are materials for state-of-the-art transistors, nanotechnology, electronic packaging, detectors, emitters, metallization, superconductivity, and energy applications. Review papers on current topics enable individuals in the field of electronics to keep abreast of activities in areas peripheral to their own. JEM also selects papers from conferences such as the Electronic Materials Conference, the U.S. Workshop on the Physics and Chemistry of II-VI Materials, and the International Conference on Thermoelectrics. It benefits both specialists and non-specialists in the electronic materials field. A journal of The Minerals, Metals & Materials Society.
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