Hui Jin , Xiaoyang Xu , Zhaohao Wang , Siyu Chen , Jing Guo , Bi Wang
{"title":"用于 MRAM 应用的新型大突发纠错拉丁平方矩阵码","authors":"Hui Jin , Xiaoyang Xu , Zhaohao Wang , Siyu Chen , Jing Guo , Bi Wang","doi":"10.1016/j.microrel.2024.115505","DOIUrl":null,"url":null,"abstract":"<div><p>With the scaling down of the technology node of complementary metal–oxide–semiconductor (CMOS) , the bit error rate (BER) of magnetic random memory (MRAM) seriously threats the reliability, especially multiple-cell upset (MBUs). Error correction codes (ECCs) such as one-step majority logic decodable (OS-MLD) codes are proposed with strong error correction capabilities, and efficient hardware overhead. However, the OS-MLD codes are not suitable for the burst error correction, which require more redundancy bits or extra memory cells. A novel m order Latin square matrix (LSM) codes for MRAM are presented, which can provide fewer equivalent bits and more flexible adjustments for correcting large burst errors. The 5-bit LSM code area is only 90898.71 <span><math><mrow><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>, and the power consumption is only 0.82 mw.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115505"},"PeriodicalIF":1.6000,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Novel Latin square matrix code of large burst error correction for MRAM applications\",\"authors\":\"Hui Jin , Xiaoyang Xu , Zhaohao Wang , Siyu Chen , Jing Guo , Bi Wang\",\"doi\":\"10.1016/j.microrel.2024.115505\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>With the scaling down of the technology node of complementary metal–oxide–semiconductor (CMOS) , the bit error rate (BER) of magnetic random memory (MRAM) seriously threats the reliability, especially multiple-cell upset (MBUs). Error correction codes (ECCs) such as one-step majority logic decodable (OS-MLD) codes are proposed with strong error correction capabilities, and efficient hardware overhead. However, the OS-MLD codes are not suitable for the burst error correction, which require more redundancy bits or extra memory cells. A novel m order Latin square matrix (LSM) codes for MRAM are presented, which can provide fewer equivalent bits and more flexible adjustments for correcting large burst errors. The 5-bit LSM code area is only 90898.71 <span><math><mrow><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>, and the power consumption is only 0.82 mw.</p></div>\",\"PeriodicalId\":51131,\"journal\":{\"name\":\"Microelectronics Reliability\",\"volume\":\"162 \",\"pages\":\"Article 115505\"},\"PeriodicalIF\":1.6000,\"publicationDate\":\"2024-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0026271424001859\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271424001859","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Novel Latin square matrix code of large burst error correction for MRAM applications
With the scaling down of the technology node of complementary metal–oxide–semiconductor (CMOS) , the bit error rate (BER) of magnetic random memory (MRAM) seriously threats the reliability, especially multiple-cell upset (MBUs). Error correction codes (ECCs) such as one-step majority logic decodable (OS-MLD) codes are proposed with strong error correction capabilities, and efficient hardware overhead. However, the OS-MLD codes are not suitable for the burst error correction, which require more redundancy bits or extra memory cells. A novel m order Latin square matrix (LSM) codes for MRAM are presented, which can provide fewer equivalent bits and more flexible adjustments for correcting large burst errors. The 5-bit LSM code area is only 90898.71 , and the power consumption is only 0.82 mw.
期刊介绍:
Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged.
Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.