A SEGR hardened trench gate DMOS with stepped source and optimized LOCOS structure

When irradiation experiment with heavy ions is carried out, Single-Event Gate Rupture (SEGR) is found for the conventional trench-gate DMOS (TG-DMOS) with LOCOS (Local Oxidation of Silicon). FIB analysis show that the failure spot is at the corner of the trench, which is the weakest point of the trench. In this paper, a SEGR hardened TG-DMOS with stepped source and optimized LOCOS structure is proposed. Stepped source is adopted to obtain a narrow base region and less voltage drop when the minority holes travel through the base region, which alleviates the electric field in the trench corner. Optimized LOCOS structure includes local oxidation area not only at the bottom of the gate trench but also at partial sidewall of the trench near the corner, protecting the trench corner and have no effect on the electrical characteristic. For the proposed structure, simulation shows that the peak electric field in the gate oxide is 3.8 MV/cm, which is almost half of the conventional TG-DMOS, and SEGR performance could be improved effectively.