Study of A Heterojunction Double Gate Ferroelectric p-n-i-n Tunnel FET combining analytical modeling and TCAD simulation

A short channel Heterojunction Double Gate Ferroelectric p-n-i-n Tunnel Field Effect Transistor structure is proposed in this article to alleviate undesirable ambipolarity and Miller Capacitance and has a steeper subthreshold swing with improvement in ON state current compared to other conventional TFET structures. This work develops a physics based relevant analytical model of surface potential with the effect of gate fringing field and inclusive source and channel depletion region, drain current model, terminal charge and capacitance model to investigate its transient performance for the impact of ferroelectric polarization according to the Miller Ferroelectric polarization model. The proposed device is also validated using the SILVACO ATLAS device simulator, which yields a good agreement with the model, establishing its reliability and acceptability. The device achieves a steeper subthreshold of 31.3 mV/decade, an improved ON current $\sim$ 5.9 x 10⁻⁴ A/ $\mu m$ and enhanced transconductance $\sim$ 0.105 ms as well as a very low energy delay product (EDP) $\sim$ 4.07 x 10⁻³ Js with hysteresis free operation at a low supply voltage $\sim$ 0.5 V in a 40 nm technology node, making it desirable for ultra-low power analog and logic applications.