Numerical simulation of core shell dual metal gate stack junctionless accumulation mode nanowire FET (CS-DM-GS-JAMNWFET) for low power digital applications

In this paper, Core Shell Dual Metal Gate Stack Junctionless Accumulation Mode Nanowire FET (CS-DM-GS-JAMNWFET) is proposed, which has enhanced performance and is suitable for analog and digital applications. A high-k gate stack engineering, Hafnium Oxide (HfO₂) is deployed in the outer as well as inner gate oxides of the core shell structure. The proposed device is compared with CS-DM-JAMNWFET, CS-SM-JAMNWFET, DM-GS-JAMNWFET, DM-JAMNWFET, and SM-JAMNWFET by maintaining a constant threshold voltage for all structures. The proposed CS-DM-GS-JAMNWFET provides a substantial reduction in subthreshold current with a high I_on/I_off ratio as compared to other competent device structures. Also, the proposed device exhibits improvements in various parameters compared to the SM-JAMNWFET. It shows improvement in drain current (2.27 times), output conductance (2.14 times), subthreshold swing (0.94 times), transconductance (2.47 times), gate capacitance (2.00 times), cut-off frequency (1.24 times), intrinsic gain (12.95 times), current gain (1.46), I_on/I_off ratio (6.15 times), unilateral power gain (1.09 times), maximum transducer power gain (1.08 times), Transconductance Generation factor (1.08 times), gain frequency product (14.61 times), transconductance frequency product (1.32 times), and gain transconductance frequency product (17.27 times). These benefits are due to combined advantages of the dual metal high-k dielectric HfO₂ structure in core shell JAM FET, which enhances the device's gate dominance over the channel with high driving current.