{"title":"在20nm技术下使用不同逻辑样式的基于DSIG JLT的多路复用器和多路分解器的有效实现","authors":"Neha Garg, Yogesh Pratap, Sneha Kabra","doi":"10.1007/s10825-023-02099-5","DOIUrl":null,"url":null,"abstract":"<div><p>The aim of this paper is to propose a compact device to design a multiplexer and demultiplexer which can reduce the circuit area while maintaining competitive performance. A novel device, the dielectric-separated independent-gate junctionless transistor (DSIG-JLT), is used to implement functional logic of a multiplexer and demultiplexer. The DSIG-JLT has four gates that can be electrically controlled in multiple ways to realize different digital logics. The DSIG-JLT is used to realize a 2 × 1 multiplexer and 1 × 2 demultiplexer by two different logic styles. The 2 × 1 multiplexer is implemented using four transistors, and the 1 × 2 demultiplexer is implemented using five transistors by NAND logic (logic style-1). Further, by using mixed logic, the 2 × 1 multiplexer is designed using three transistors, and the 1 × 2 demultiplexer using four transistors (logic style-2). A 4 × 1 multiplexer is also implemented using eight transistors. The propagation delay, rise time, and fall time of the 2 × 1 multiplexer (logic style-1) are calculated and are found to be 24.45 ps, 31 ps, and 8.2 ps, respectively, at a supply voltage (<i>V</i><sub>DD</sub>) of 1 V. It is found that with a change in supply voltage from 0.7 to 1.0 V, the delay, rise time, and fall time decrease by 17.2%, 11.4%, and 65.69%, respectively. Simulations are carried using the ATLAS 3D device simulator in mixed mode.</p><h3>Graphical abstract</h3>\n <div><figure><div><div><picture><source><img></source></picture></div></div></figure></div>\n </div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":null,"pages":null},"PeriodicalIF":2.2000,"publicationDate":"2023-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Efficient implementation of a DSIG-JLT-based multiplexer and demultiplexer using different logic styles at 20-nm technology\",\"authors\":\"Neha Garg, Yogesh Pratap, Sneha Kabra\",\"doi\":\"10.1007/s10825-023-02099-5\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>The aim of this paper is to propose a compact device to design a multiplexer and demultiplexer which can reduce the circuit area while maintaining competitive performance. A novel device, the dielectric-separated independent-gate junctionless transistor (DSIG-JLT), is used to implement functional logic of a multiplexer and demultiplexer. The DSIG-JLT has four gates that can be electrically controlled in multiple ways to realize different digital logics. The DSIG-JLT is used to realize a 2 × 1 multiplexer and 1 × 2 demultiplexer by two different logic styles. The 2 × 1 multiplexer is implemented using four transistors, and the 1 × 2 demultiplexer is implemented using five transistors by NAND logic (logic style-1). Further, by using mixed logic, the 2 × 1 multiplexer is designed using three transistors, and the 1 × 2 demultiplexer using four transistors (logic style-2). A 4 × 1 multiplexer is also implemented using eight transistors. The propagation delay, rise time, and fall time of the 2 × 1 multiplexer (logic style-1) are calculated and are found to be 24.45 ps, 31 ps, and 8.2 ps, respectively, at a supply voltage (<i>V</i><sub>DD</sub>) of 1 V. It is found that with a change in supply voltage from 0.7 to 1.0 V, the delay, rise time, and fall time decrease by 17.2%, 11.4%, and 65.69%, respectively. Simulations are carried using the ATLAS 3D device simulator in mixed mode.</p><h3>Graphical abstract</h3>\\n <div><figure><div><div><picture><source><img></source></picture></div></div></figure></div>\\n </div>\",\"PeriodicalId\":620,\"journal\":{\"name\":\"Journal of Computational Electronics\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2023-10-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Computational Electronics\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s10825-023-02099-5\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Computational Electronics","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10825-023-02099-5","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Efficient implementation of a DSIG-JLT-based multiplexer and demultiplexer using different logic styles at 20-nm technology
The aim of this paper is to propose a compact device to design a multiplexer and demultiplexer which can reduce the circuit area while maintaining competitive performance. A novel device, the dielectric-separated independent-gate junctionless transistor (DSIG-JLT), is used to implement functional logic of a multiplexer and demultiplexer. The DSIG-JLT has four gates that can be electrically controlled in multiple ways to realize different digital logics. The DSIG-JLT is used to realize a 2 × 1 multiplexer and 1 × 2 demultiplexer by two different logic styles. The 2 × 1 multiplexer is implemented using four transistors, and the 1 × 2 demultiplexer is implemented using five transistors by NAND logic (logic style-1). Further, by using mixed logic, the 2 × 1 multiplexer is designed using three transistors, and the 1 × 2 demultiplexer using four transistors (logic style-2). A 4 × 1 multiplexer is also implemented using eight transistors. The propagation delay, rise time, and fall time of the 2 × 1 multiplexer (logic style-1) are calculated and are found to be 24.45 ps, 31 ps, and 8.2 ps, respectively, at a supply voltage (VDD) of 1 V. It is found that with a change in supply voltage from 0.7 to 1.0 V, the delay, rise time, and fall time decrease by 17.2%, 11.4%, and 65.69%, respectively. Simulations are carried using the ATLAS 3D device simulator in mixed mode.
期刊介绍:
he Journal of Computational Electronics brings together research on all aspects of modeling and simulation of modern electronics. This includes optical, electronic, mechanical, and quantum mechanical aspects, as well as research on the underlying mathematical algorithms and computational details. The related areas of energy conversion/storage and of molecular and biological systems, in which the thrust is on the charge transport, electronic, mechanical, and optical properties, are also covered.
In particular, we encourage manuscripts dealing with device simulation; with optical and optoelectronic systems and photonics; with energy storage (e.g. batteries, fuel cells) and harvesting (e.g. photovoltaic), with simulation of circuits, VLSI layout, logic and architecture (based on, for example, CMOS devices, quantum-cellular automata, QBITs, or single-electron transistors); with electromagnetic simulations (such as microwave electronics and components); or with molecular and biological systems. However, in all these cases, the submitted manuscripts should explicitly address the electronic properties of the relevant systems, materials, or devices and/or present novel contributions to the physical models, computational strategies, or numerical algorithms.