具有动态功率门控的自适应时钟，可减轻22nm图形执行核心中快速电压下降对能效和性能的影响

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573529

M. Cho, Carlos Tokunaga, Stephen T. Kim, J. Tschanz, M. Khellah, V. De

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引用次数: 3

摘要

以最佳方式将自适应时钟与动态功率门控相结合，可以比单独使用自适应时钟更有效地减轻22nm图形执行核心中快速电源电压下降的能效和性能影响。测量结果表明，存在一个最佳的VMIN，其中组合提供了最佳的改进-在890MHz时能量降低14%，而自适应时钟降低4%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core

Combining adaptive clocking with dynamic power gating in an optimal manner mitigates energy efficiency and performance impacts of fast supply voltage droop in a 22nm graphics execution core more effectively than adaptive clocking alone. Measurements show that there is an optimal VMIN where the combination provides the best improvement - 14% lower energy at 890MHz vs. 4% with adaptive clocking.

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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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