Anna W. Topol, D. La Tulipe, L. Shi, S. Alam, D. Frank, S. Steen, J. Vichiconti, D. Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D. Dimilia, M. Robson, E. Duch, M. Farinelli, C. Wang, R. Conti, D. Canaperi, L. Deligianni, A. Kumar, K. Kwietniak, C. D'Emic, J. Ott, A. Young, K. Guarini, M. Ieong
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引用次数: 91
摘要
我们针对三维(3D)集成电路(ic)的关键工艺技术挑战提出了解决方案，这些解决方案能够创建堆叠器件层，它们之间的距离最短，互连密度最高，晶圆对晶圆对齐非常积极。为了实现这一重要的3D集成电路技术里程碑，我们优化了层转移工艺，包括玻璃手柄晶圆、氧化物熔合、晶圆弓补偿方法，以及用于在两个堆叠器件层之间创建高宽高比(6:1 < AR < 11:1)接触的单大马士革图案和金属化方法
Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)
We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment. To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene patterning and metallization method for creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers
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