An In-Situ Sliding Window Approximate Inner-Product Scheme Based on Parallel Distributed Arithmetic for Ultra-Low Power Fault-Tolerant Applications

Approximate computing (AC) provides an efficient solution for reducing power, area, and complexity of digital systems. When backed with distributed arithmetic (DA), AC leverages the ability to implement ultra-efficient inner-product units in terms of area, power, and delay. Such units can be used in any inherently resilient application. This paper presents a novel scheme of approximate inner-product based on parallel DA for low-power fault-tolerant applications backed with a novel in-situ sliding window algorithm. Our model eliminates the need for an explicit error correction scheme, which further reduces the overhead while improving the accuracy. The experimental results show that our model achieves a state-of-the-art performance in terms of power delay product (PDP), area power product (APP) with a reduction of 39.26% and 48.83%, respectively.