集成射频电源应用中65nm CMOS的性能和限制

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI:10.1109/IEDM.2005.1609353

J. Scholvin, D. Greenberg, J. D. del Alamo

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引用次数: 15

摘要

在这项研究中，我们首次测量了65nm CMOS在不同电压和布局下的射频功率性能。我们证明了65nm技术节点能够在8ghz下实现大于50%的PAE值，Pout可扩展到约17dbm。这是许多应用程序都感兴趣的。通过优化布局以最小化互连电阻，期望获得更高的性能

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Performance and limitations of 65 nm CMOS for integrated RF power applications

In this study, we present the first measurements of the RF power performance of 65 nm CMOS for different voltages and layouts. We demonstrate that the 65 nm technology node is capable of achieving PAE values greater than 50% at 8 GHz, with Pout scalable to about 17 dBm. This is of interest for many applications. Greater performance is expected by optimizing the layout to minimize interconnect resistance

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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

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