超低电压应用的28nm FDSOI技术sub-0.6V SRAM Vmin评估

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573512

R. Ranica, N. Planes, V. Huard, O. Weber, D. Noblet, D. Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars, A. Villaret, M. Parra, S. Haendler, M. Quoirin, F. Cacho, C. Julien, F. Terrier, L. Ciampolini, D. Turgis, C. Lecocq, F. Arnaud

{"title":"超低电压应用的28nm FDSOI技术sub-0.6V SRAM Vmin评估","authors":"R. Ranica, N. Planes, V. Huard, O. Weber, D. Noblet, D. Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars, A. Villaret, M. Parra, S. Haendler, M. Quoirin, F. Cacho, C. Julien, F. Terrier, L. Ciampolini, D. Turgis, C. Lecocq, F. Arnaud","doi":"10.1109/VLSIC.2016.7573512","DOIUrl":null,"url":null,"abstract":"Vmin measurements in 28nm FDSOI technology on 128Mb SRAM bitcells from -40°C to 125°C are reported in this paper. Adding the silicon ageing behavior and the process variability, we have developed a complete model and demonstrated end-of-life SRAM Vmin of 0.6V and 0.5V on 20Mb with 0.120μm2 and 0.152μm2 bitcells, respectively. This is the first report of a such extensive SRAM Vmin assessment at the 28nm node. The construction of write limited bitcells, combined with write assist design technique, was found to be the most efficient way to achieve ultra low Vmin in 28nm FDSOI technology. In addition, Vmin retention below 0.4V is demonstrated in 0.120μm2 bitcells, leading to the enablement of ultra-low leakage bitcells with 2pA/cell in retention mode.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"142 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications\",\"authors\":\"R. Ranica, N. Planes, V. Huard, O. Weber, D. Noblet, D. Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars, A. Villaret, M. Parra, S. Haendler, M. Quoirin, F. Cacho, C. Julien, F. Terrier, L. Ciampolini, D. Turgis, C. Lecocq, F. Arnaud\",\"doi\":\"10.1109/VLSIC.2016.7573512\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Vmin measurements in 28nm FDSOI technology on 128Mb SRAM bitcells from -40°C to 125°C are reported in this paper. Adding the silicon ageing behavior and the process variability, we have developed a complete model and demonstrated end-of-life SRAM Vmin of 0.6V and 0.5V on 20Mb with 0.120μm2 and 0.152μm2 bitcells, respectively. This is the first report of a such extensive SRAM Vmin assessment at the 28nm node. The construction of write limited bitcells, combined with write assist design technique, was found to be the most efficient way to achieve ultra low Vmin in 28nm FDSOI technology. In addition, Vmin retention below 0.4V is demonstrated in 0.120μm2 bitcells, leading to the enablement of ultra-low leakage bitcells with 2pA/cell in retention mode.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"142 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573512\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 9

摘要

本文报道了28nm FDSOI技术在128Mb SRAM位单元上从-40°C到125°C的Vmin测量。考虑到硅的老化行为和工艺变化，我们建立了一个完整的模型，并在0.120μm2和0.152μm2的比特单元上分别演示了0.6V和0.5V的寿命终止SRAM Vmin。这是第一次在28nm节点上进行如此广泛的SRAM Vmin评估。在28nm FDSOI技术中，构建写限制位单元，结合写辅助设计技术，是实现超低Vmin的最有效方法。此外，在0.120μm2的位电池中，Vmin保持在0.4V以下，从而实现了2pA/cell的超低漏位电池保持模式。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications

Vmin measurements in 28nm FDSOI technology on 128Mb SRAM bitcells from -40°C to 125°C are reported in this paper. Adding the silicon ageing behavior and the process variability, we have developed a complete model and demonstrated end-of-life SRAM Vmin of 0.6V and 0.5V on 20Mb with 0.120μm2 and 0.152μm2 bitcells, respectively. This is the first report of a such extensive SRAM Vmin assessment at the 28nm node. The construction of write limited bitcells, combined with write assist design technique, was found to be the most efficient way to achieve ultra low Vmin in 28nm FDSOI technology. In addition, Vmin retention below 0.4V is demonstrated in 0.120μm2 bitcells, leading to the enablement of ultra-low leakage bitcells with 2pA/cell in retention mode.

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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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