Optimization of select gate transistor in advanced 3D NAND memory cell

There are several device challenges unique to the select gate transistor in 3D NAND memory cell. It requires low leakage current to prevent read and program disturb problem and it needs to provide enough current during read and erase operation. In this paper, we examined the design optimization of select gate transistor with respect to various device elements including work-function, S/D overlap, and trap density. Finally, we reviewed the path to reduce the channel length of the select gate transistor in conjunction with the role of dummy cells.