{"title":"设计一种高速RSA加密处理器，内置冗余二进制数残数计算表","authors":"N. Tomabechi, T. Ito","doi":"10.1109/ISCAS.2000.857583","DOIUrl":null,"url":null,"abstract":"This paper proposes a design method of a high-speed RSA encryption processor in which the residue calculation of the redundant binary numbers is realized by table-look-up method where the table is built in the hardware, It is demonstrated that the number of gates through the critical path determining the operation speed of the proposed processor is 1/62 that of the conventional processors.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers\",\"authors\":\"N. Tomabechi, T. Ito\",\"doi\":\"10.1109/ISCAS.2000.857583\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a design method of a high-speed RSA encryption processor in which the residue calculation of the redundant binary numbers is realized by table-look-up method where the table is built in the hardware, It is demonstrated that the number of gates through the critical path determining the operation speed of the proposed processor is 1/62 that of the conventional processors.\",\"PeriodicalId\":6422,\"journal\":{\"name\":\"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2000.857583\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2000.857583","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers
This paper proposes a design method of a high-speed RSA encryption processor in which the residue calculation of the redundant binary numbers is realized by table-look-up method where the table is built in the hardware, It is demonstrated that the number of gates through the critical path determining the operation speed of the proposed processor is 1/62 that of the conventional processors.
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