纳米磁体逻辑的收缩结构与应用

M. Niemier, X. Ju, M. Becherer, G. Csaba, X. Hu, Doris Schmitt-Landsiedel, Paolo Lugli, W. Porod
{"title":"纳米磁体逻辑的收缩结构与应用","authors":"M. Niemier, X. Ju, M. Becherer, G. Csaba, X. Hu, Doris Schmitt-Landsiedel, Paolo Lugli, W. Porod","doi":"10.1109/SNW.2012.6243329","DOIUrl":null,"url":null,"abstract":"Most NML research has studied small magnet ensembles for interconnect or isolated gates. We discuss how NML might be used to process information, as well as suitable system architecture-to-device architecture mappings. A case study for pattern matching hardware is presented.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Systolic architectures and applications for nanomagnet logic\",\"authors\":\"M. Niemier, X. Ju, M. Becherer, G. Csaba, X. Hu, Doris Schmitt-Landsiedel, Paolo Lugli, W. Porod\",\"doi\":\"10.1109/SNW.2012.6243329\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Most NML research has studied small magnet ensembles for interconnect or isolated gates. We discuss how NML might be used to process information, as well as suitable system architecture-to-device architecture mappings. A case study for pattern matching hardware is presented.\",\"PeriodicalId\":6402,\"journal\":{\"name\":\"2012 IEEE Silicon Nanoelectronics Workshop (SNW)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE Silicon Nanoelectronics Workshop (SNW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SNW.2012.6243329\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SNW.2012.6243329","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

摘要

大多数NML研究都是研究用于互连门或隔离门的小磁体集成。我们讨论了如何使用NML来处理信息,以及合适的系统架构到设备架构映射。给出了一个模式匹配硬件的实例研究。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Systolic architectures and applications for nanomagnet logic
Most NML research has studied small magnet ensembles for interconnect or isolated gates. We discuss how NML might be used to process information, as well as suitable system architecture-to-device architecture mappings. A case study for pattern matching hardware is presented.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Statistical variability study of a 10nm gate length SOI FinFET device A novel gate-all-around ultra-thin p-channel poly-Si TFT functioning as transistor and flash memory with silicon nanocrystals Quantum transport property in FETs with deterministically implanted single-arsenic ions using single-ion implantation Graphene fillers for ultra-efficient thermal interface materials Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1