Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243319
M. H. Cho, W. Kwon, N. Xu, T. K. Liu
The scaling limit of the BJT-based capacitorless DRAM cell is investigated via 3-D process and device simulations, accounting for systematic and random sources of variation. The cell design and operating voltages are optimized at each gate length, following a constant electric field methodology. Retention time decreases with gate length, so that the scaling limit is expected to be 16.5 nm or 13 nm, depending on the application.
{"title":"Variation-aware study of BJT-based capacitorless DRAM cell scaling limit","authors":"M. H. Cho, W. Kwon, N. Xu, T. K. Liu","doi":"10.1109/SNW.2012.6243319","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243319","url":null,"abstract":"The scaling limit of the BJT-based capacitorless DRAM cell is investigated via 3-D process and device simulations, accounting for systematic and random sources of variation. The cell design and operating voltages are optimized at each gate length, following a constant electric field methodology. Retention time decreases with gate length, so that the scaling limit is expected to be 16.5 nm or 13 nm, depending on the application.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"48 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74678485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243301
Gai Liu, G. Du, Tiao Lu, Xiaoyan Liu, Pingwen Zhang, Xing Zhang
Quasi-ballistic asymmetric DG-MOSFET has been simulated using a multi-subband Boltzmann transport equation solver and important parameters regarding to back-scattering at the top of barrier are carefully studied in this work. It is observed that the simulated results are in good agreement with established theory and phonon scattering still plays an important role in limiting the performance of MOSFET even when gate length is scaled down to sub-10nm.
{"title":"Evaluation of scattering in asymmetric quasi-ballistic DG-MOSFET","authors":"Gai Liu, G. Du, Tiao Lu, Xiaoyan Liu, Pingwen Zhang, Xing Zhang","doi":"10.1109/SNW.2012.6243301","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243301","url":null,"abstract":"Quasi-ballistic asymmetric DG-MOSFET has been simulated using a multi-subband Boltzmann transport equation solver and important parameters regarding to back-scattering at the top of barrier are carefully studied in this work. It is observed that the simulated results are in good agreement with established theory and phonon scattering still plays an important role in limiting the performance of MOSFET even when gate length is scaled down to sub-10nm.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"34 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75602327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243343
B. Cheng, A. Brown, Xingsheng Wang, A. Asenov
A comprehensive statistical variability simulation study of a 10nm gate length FinFET device is presented. The FER-induced quantum confinement variation has a consistent impact on all device operation regions; while the RDD induced S/D resistance variation has little impact on the sub-threshold, but has relatively strong impact on the on-current, which is in contrast with the impact of GER on device characteristics. The statistical reliability simulation results indicate that the impact of NBTI/PBTI on individual device is the combined results of trap and fin configurations. Both statistical variability and reliability simulations demonstrate some degree of disentangling between sub-threshold and on-current behaviour. The advantage of FinFET technology is demonstrated by the result of statistical SRAM cell simulation.
{"title":"Statistical variability study of a 10nm gate length SOI FinFET device","authors":"B. Cheng, A. Brown, Xingsheng Wang, A. Asenov","doi":"10.1109/SNW.2012.6243343","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243343","url":null,"abstract":"A comprehensive statistical variability simulation study of a 10nm gate length FinFET device is presented. The FER-induced quantum confinement variation has a consistent impact on all device operation regions; while the RDD induced S/D resistance variation has little impact on the sub-threshold, but has relatively strong impact on the on-current, which is in contrast with the impact of GER on device characteristics. The statistical reliability simulation results indicate that the impact of NBTI/PBTI on individual device is the combined results of trap and fin configurations. Both statistical variability and reliability simulations demonstrate some degree of disentangling between sub-threshold and on-current behaviour. The advantage of FinFET technology is demonstrated by the result of statistical SRAM cell simulation.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"207 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72664036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243303
O. Badami, N. Kumar, D. Saha, S. Ganguly
Multiple gate MOSFETs (MuGFET) have gained significant attention as the scaling of the conventional MOSFET comes to an end. Of the possible architectures, the gate-all-around nanowire (NW) transistor offers the best gate control over the channel. In order to model GAA nanowire devices for channel lengths less than 10nm, while preserving a connection to the drift-diffusion framework familiar to device engineers, we have developed a quantum-corrected transport simulator that includes Quantum Drift-Diffusion (QDD) and Quantum Energy Balance (QEB). This formalism is applied to the example of the NW junctionless transistor (JLT), an interesting modification to the NW-MOSFET obtained by replacing the n+-p-n+ structure by a bar of n+ region, that promises smaller variability.
{"title":"Quantum Drift-Diffusion and Quantum Energy Balance simulation of nanowire junctionless transistors","authors":"O. Badami, N. Kumar, D. Saha, S. Ganguly","doi":"10.1109/SNW.2012.6243303","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243303","url":null,"abstract":"Multiple gate MOSFETs (MuGFET) have gained significant attention as the scaling of the conventional MOSFET comes to an end. Of the possible architectures, the gate-all-around nanowire (NW) transistor offers the best gate control over the channel. In order to model GAA nanowire devices for channel lengths less than 10nm, while preserving a connection to the drift-diffusion framework familiar to device engineers, we have developed a quantum-corrected transport simulator that includes Quantum Drift-Diffusion (QDD) and Quantum Energy Balance (QEB). This formalism is applied to the example of the NW junctionless transistor (JLT), an interesting modification to the NW-MOSFET obtained by replacing the n+-p-n+ structure by a bar of n+ region, that promises smaller variability.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"7 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80927958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243351
Yahua Peng, Xiaoyan Liu, G. Du, Yan Yang, Jinfeng Kang
A simulation method for evaluating the performance of CTM with incorporating nanocrystals into the charge trap layer is presented and the effects of bias voltage, charge trap distribution, nanocrystal size, temperature and gate dielectric layer's thickness on program/erase/retention characteristic are studied. It can be a useful tool for designing nanocrystals based CTM.
{"title":"Simulation of charge trapping memory with silicon nanocrystals embedded in silicon nitride layer","authors":"Yahua Peng, Xiaoyan Liu, G. Du, Yan Yang, Jinfeng Kang","doi":"10.1109/SNW.2012.6243351","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243351","url":null,"abstract":"A simulation method for evaluating the performance of CTM with incorporating nanocrystals into the charge trap layer is presented and the effects of bias voltage, charge trap distribution, nanocrystal size, temperature and gate dielectric layer's thickness on program/erase/retention characteristic are studied. It can be a useful tool for designing nanocrystals based CTM.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"14 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84595241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243323
B. Liu, X. Gong, G. Han, P. S. Lim, Y. Tong, Qian Zhou, Yue Yang, N. Daval, M. Pulido, D. Delprat, B. Nguyen, Y. Yeo
We report the first Ω-gate Germanium (Ge) p-channel FinFET with low-temperature Si2H6 passivation and implantless Schottky-barrier nickel germanide (NiGe) metallic Source/Drain, formed on high-quality GeOI substrates using sub-400 °C process modules. As compared with reported multi-gate (MuG) Ge devices in which the Ge channels were formed by top-down approaches, the Ge FinFETs in this work have a record high on-state current ION of ~494 μA/μm at VGS - VTH = -1 V and VDS = -1 V. A high ION/IOFF ratio of more than 3×104 and a high peak saturation transconductance GMSatMax of ~540 μS/μm were achieved.
{"title":"High performance Ω-gate Ge FinFET featuring low temperature Si2H6 passivation and implantless Schottky-barrier NiGe metallic Source/Drain","authors":"B. Liu, X. Gong, G. Han, P. S. Lim, Y. Tong, Qian Zhou, Yue Yang, N. Daval, M. Pulido, D. Delprat, B. Nguyen, Y. Yeo","doi":"10.1109/SNW.2012.6243323","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243323","url":null,"abstract":"We report the first Ω-gate Germanium (Ge) p-channel FinFET with low-temperature Si<sub>2</sub>H<sub>6</sub> passivation and implantless Schottky-barrier nickel germanide (NiGe) metallic Source/Drain, formed on high-quality GeOI substrates using sub-400 °C process modules. As compared with reported multi-gate (MuG) Ge devices in which the Ge channels were formed by top-down approaches, the Ge FinFETs in this work have a record high on-state current I<sub>ON</sub> of ~494 μA/μm at V<sub>GS</sub> - V<sub>TH</sub> = -1 V and V<sub>DS</sub> = -1 V. A high I<sub>ON</sub>/I<sub>OFF</sub> ratio of more than 3×10<sup>4</sup> and a high peak saturation transconductance G<sub>MSatMax</sub> of ~540 μS/μm were achieved.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76970089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243298
D. Moraru, Y. Kuzuya, E. Hamid, T. Mizuno, M. Tabe, H. Mizuta
We analyzed by ab initio atomistic simulations the energy spectrum of individual donors in Si nanostructures and found significantly enhanced ionization energy (~ 1 eV). By correlating these findings to experimental measurements of doped nanoscale SOI-FETs, design rules can be clarified for tunneling operation of single-dopant devices towards room temperature.
{"title":"Ab initio analysis of donor state deepening in Si nano-channels","authors":"D. Moraru, Y. Kuzuya, E. Hamid, T. Mizuno, M. Tabe, H. Mizuta","doi":"10.1109/SNW.2012.6243298","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243298","url":null,"abstract":"We analyzed by ab initio atomistic simulations the energy spectrum of individual donors in Si nanostructures and found significantly enhanced ionization energy (~ 1 eV). By correlating these findings to experimental measurements of doped nanoscale SOI-FETs, design rules can be clarified for tunneling operation of single-dopant devices towards room temperature.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"13 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90189143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243315
S. Migita, K. Fukuda, Y. Morita, H. Ota
Temperature dependences of tunnel field-effect transistor (TFET) and MOSFET were experimentally compared on the same SOI wafer. Validity of the TFET result was corroborated by simulation. It is demonstrated that VTH shift and off-current increment of Si-TFET with temperature were smaller in comparison with Si-MOSFET. Temperature stability of TFET is promising for ultra-low power VLSI.
{"title":"Experimental demonstration of temperature stability of Si-tunnel FET over Si-MOSFET","authors":"S. Migita, K. Fukuda, Y. Morita, H. Ota","doi":"10.1109/SNW.2012.6243315","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243315","url":null,"abstract":"Temperature dependences of tunnel field-effect transistor (TFET) and MOSFET were experimentally compared on the same SOI wafer. Validity of the TFET result was corroborated by simulation. It is demonstrated that VTH shift and off-current increment of Si-TFET with temperature were smaller in comparison with Si-MOSFET. Temperature stability of TFET is promising for ultra-low power VLSI.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"3 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89444593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243295
E. González-Marín, F. Ruiz, A. Godoy, I. M. Tienda-Luna, F. Gámiz
This work studies the influence of the interfacial states on the performance of Trigate MOSFETs and, specifically, on the Subthreshold Swing (SS) and threshold voltage (VT) variability. To do so, a solver for the 2D Schrödinger-Poisson coupled equation system has been developed, including the effects of interfacial states (Dit). Different Dit(E) profiles have been considered, analyzing their influence for several device geometries.
{"title":"Effect of interfacial states on the technological variability of trigate MOSFETs","authors":"E. González-Marín, F. Ruiz, A. Godoy, I. M. Tienda-Luna, F. Gámiz","doi":"10.1109/SNW.2012.6243295","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243295","url":null,"abstract":"This work studies the influence of the interfacial states on the performance of Trigate MOSFETs and, specifically, on the Subthreshold Swing (SS) and threshold voltage (VT) variability. To do so, a solver for the 2D Schrödinger-Poisson coupled equation system has been developed, including the effects of interfacial states (Dit). Different Dit(E) profiles have been considered, analyzing their influence for several device geometries.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"18 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84353789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel method of fabricate ultrathin body (UTB) junctionless TFTs (JLTFT) with sub-10nm poly-Si channel has been successfully demonstrated. It is no additional mask for lithography. The cost of fabrication flow can be reduced by a novel method, that demonstrate at this work. UTB JLTFT has low threshold voltage and steep subthreshold slop 160 mV/dec at W/L=0.7um/1um. An ON/OFF current ratio is about 106, and transconductance does not decrease rapidly at a high drain voltage.
{"title":"Fabrication and characterization of a Pi-gate ultrathin body junctionless poly-Si TFTs","authors":"Jia-Jiun Wu, Hung-Bin Chen, Ming-Hung Han, Yung-Chun Wu, Chun-Yen Chang","doi":"10.1109/SNW.2012.6243302","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243302","url":null,"abstract":"A novel method of fabricate ultrathin body (UTB) junctionless TFTs (JLTFT) with sub-10nm poly-Si channel has been successfully demonstrated. It is no additional mask for lithography. The cost of fabrication flow can be reduced by a novel method, that demonstrate at this work. UTB JLTFT has low threshold voltage and steep subthreshold slop 160 mV/dec at W/L=0.7um/1um. An ON/OFF current ratio is about 106, and transconductance does not decrease rapidly at a high drain voltage.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"42 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84540364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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