Stress optimization study about heterogeneous multi-chip structure in Fan-out Wafer Level Package Young-in, Republic of Korea

The IEEE Heterogeneous Integration Roadmap Symposium, held in 2018, emphasized the importance of integrating diverse components into a SiP and presented the challenges for SiP reliability. One of the problems in the reliability is a CTE(Coefficient of Thermal Expansion) mismatch between various CTE of heterogeneous materials. This mismatch issue can easily understand when we analysis a warpage in the package structure. Unlike traditional packages, FOWLP has the advantage that the substrate can be removed to achieve a thinner thickness and the thermal and electrical properties are superior to conventional packages. However, it is vulnerable to warpage due to its thin thickness and there is a problem with reliability due to cracks caused by the stress concentration of the solderball. So, to perform SiP multi-chip package with FOWLP, it is necessary to study stress-induced optimization. And we will study this through computer simulations and present guidelines.In this paper, we present an optimization solution by performing the stress analysis with the package area effect of the multi-chip FOWLP structure. In the analysis, the finite element modeling was performed on a 20X20 mm2 package approximately 200,000 elements and 90,000 nodes, simulating the Post Mold Cure of FOWLP. Because of changing the chip size, height and package / chip area ratio in order to understand the effect of the multi-chip on the package, it was confirmed that the larger the size difference among the multi chips in the package, the larger the warpage occurs. as the size of the chip became larger, the stress distribution became larger at the edge of the chip, and it was also confirmed that the larger the height difference between the multi chips, the larger the warpage occurred.