A 9-b 0.4-V charge-mode SAR ADC with 1.6-V input swing and a MOSCAP-only DAC

The linearity of the vast majority of the ADC topologies is limited by the linearity of the employed circuit elements, e.g. resistors and capacitors. This paper presents a 9-b charge-mode SAR ADC that uses only very nonlinear MOSCAPs as the DAC capacitance elements and still presents 67 dB of SFDR. The track-and-hold exploits the routing parasitics as the sampling capacitance, entirely obviating MOM capacitors in the design. The circuit employs local voltage boosting and a new boost-and-bootstrap switch in order to allow operation under 0.4 V of supply voltage. Still, the ADC topology achieves a differential input swing of 1.6 Vpp, which is four times the supply voltage. The 0.13-μm CMOS prototype achieves an ENOB of 8.01 at 300 kSps while consuming 354 nW. The corresponding FoM is 4.57 fJ/conversion-step.