一个2db NF,全差分,可变增益,900mhz CMOS LNA

E. Sacchi, I. Bietti, F. Gatta, F. Svelto, R. Castello
{"title":"一个2db NF,全差分,可变增益,900mhz CMOS LNA","authors":"E. Sacchi, I. Bietti, F. Gatta, F. Svelto, R. Castello","doi":"10.1109/VLSIC.2000.852860","DOIUrl":null,"url":null,"abstract":"A fully differential 900 MHz CMOS LNA using, as input stage, nMOS and pMOS inductively degenerated pairs, in shunt configuration, achieves the following performance: 2 dB NF, 22 dB voltage gain, -3 dBm IIP3 with 8 mA current consumption. As additional feature of this LNA is a variable gain. Measurements have been performed on packaged dies. No external components are used, except for an SMD inductor (used for tuning purposes), placed in series with the on-chip gate spiral inductor.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"87 1","pages":"94-97"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"31","resultStr":"{\"title\":\"A 2 dB NF, fully differential, variable gain, 900 MHz CMOS LNA\",\"authors\":\"E. Sacchi, I. Bietti, F. Gatta, F. Svelto, R. Castello\",\"doi\":\"10.1109/VLSIC.2000.852860\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully differential 900 MHz CMOS LNA using, as input stage, nMOS and pMOS inductively degenerated pairs, in shunt configuration, achieves the following performance: 2 dB NF, 22 dB voltage gain, -3 dBm IIP3 with 8 mA current consumption. As additional feature of this LNA is a variable gain. Measurements have been performed on packaged dies. No external components are used, except for an SMD inductor (used for tuning purposes), placed in series with the on-chip gate spiral inductor.\",\"PeriodicalId\":6361,\"journal\":{\"name\":\"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)\",\"volume\":\"87 1\",\"pages\":\"94-97\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"31\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2000.852860\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2000.852860","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 31

摘要

采用nMOS和pMOS电感退化对作为输入级,并联配置的全差分900 MHz CMOS LNA可实现以下性能:2 dB NF, 22 dB电压增益,-3 dBm IIP3, 8ma电流消耗。这个LNA的附加特性是可变增益。对封装的模具进行了测量。除了SMD电感器(用于调谐目的)外,不使用外部元件,与片上门螺旋电感器串联。
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A 2 dB NF, fully differential, variable gain, 900 MHz CMOS LNA
A fully differential 900 MHz CMOS LNA using, as input stage, nMOS and pMOS inductively degenerated pairs, in shunt configuration, achieves the following performance: 2 dB NF, 22 dB voltage gain, -3 dBm IIP3 with 8 mA current consumption. As additional feature of this LNA is a variable gain. Measurements have been performed on packaged dies. No external components are used, except for an SMD inductor (used for tuning purposes), placed in series with the on-chip gate spiral inductor.
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