采用40nm CMOS的14位8.9GS/s射频DAC，在2.9GHz下实现了>71dBc的LTE ACPR

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573538

V. Ravinuthula, W. Bright, M. Weaver, K. Maclean, S. Kaylor, S. Balasubramanian, Jesse Coulon, Robert Keller, B. Nguyen, E. Dwobeng

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引用次数: 20

摘要

我们首次展示了8.9 GS/s的射频电流导向DAC，具有片上1:1 Balun和8通道12.5 Gbps JESD204B兼容的SerDes，在邻近的20mhz频段测量的LTE ACPR >71 dBc，用于2.9 GHz信道。DAC具有IM3 < -65 dBc，输出频率高达奈奎斯特。这种性能是通过使用新颖的DAC开关驱动器和数据/虚拟数据方案来实现的，以最大限度地减少DAC驱动器电源和地上与模式相关的电流源/下沉。该DAC采用40nm双氧化物CMOS工艺制造，功耗为1.2W，不包括合成数字块和SerDes的贡献。

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A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz

We show for the first time an 8.9 GS/s RF current-steering DAC, with an on-chip 1:1 Balun, and an 8-lane 12.5 Gbps JESD204B compliant SerDes, with a measured LTE ACPR >71 dBc in the adjacent 20 MHz band for a 2.9 GHz channel. The DAC has IM3 <;-65 dBc for output frequencies up to Nyquist. This performance is accomplished using a novel DAC switch driver and data/dummy-data scheme to minimize the pattern dependent sourcing/sinking of current on the DAC driver supply and ground. The DAC is fabricated in a 40nm dual-oxide CMOS process and dissipates 1.2W, with the contribution of the synthesized digital block and SerDes excluded.

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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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