Repeater insertion in deep sub-micron CMOS: ramp-based analytical model and placement sensitivity analysis

Repeaters are now widely used to increase the performance of long on-chip interconnections in CMOS VLSI. In this paper, we take an updated look at repeater insertion in state-of-the-art CMOS, using a new more detailed model. In spite of the more complex model, we present closed form expressions for the delay and the optimal repeater spacing and sizing. Our model is based on the alpha-power law to account for the short-channel effects and resistive loads that arise in deep sub-micron technologies. Unlike previous work, we model the repeater input as a ramp and accurately model both linear and saturation regions of operation for estimating the propagation delay. Our analytical repeater model is applied for estimating the performance of driving various repeated RC loads and exhibits a maximum error of only 5% when compared with SPICE in a 0.13 /spl mu/m CMOS technology. In practice, it is not always feasible to insert the repeaters at the exact optimal locations along an interconnect. We present a placement sensitivity analysis to quantify the effect of the sub-optimal repeater placement on performance. Closed form expressions are derived to re-size the repeaters to compensate for the sub-optimal placement.