Il-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Y. Jang, Y. Cho, Y. Sohn, J. Choi, Seong-Jin Jang, Byungsub Kim, J. Sim, Hong-June Park
{"title":"采用三电平平衡编码方案的低emi四位四线单端DRAM接口","authors":"Il-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Y. Jang, Y. Cho, Y. Sohn, J. Choi, Seong-Jin Jang, Byungsub Kim, J. Sim, Hong-June Park","doi":"10.1109/VLSIC.2016.7573524","DOIUrl":null,"url":null,"abstract":"The measured H-field EMI peak was reduced by around 15dB in a 4-wire single-ended DRAM interface by using a 3-level balanced coding scheme with a 100% pin efficiency. Charge-pump circuits are used to generate 3-level channel signals (-100mV, 0, +100mV) at TX. The RX input comparator uses the ground-level (0) as the voltage reference and employs the meta-stability to identify the ground-level input. The energy efficiency was 2.67pJ/b at 6.4Gb/s with a 65nm LP 1.2V CMOS process and 3-inch FR-4.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"45 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme\",\"authors\":\"Il-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Y. Jang, Y. Cho, Y. Sohn, J. Choi, Seong-Jin Jang, Byungsub Kim, J. Sim, Hong-June Park\",\"doi\":\"10.1109/VLSIC.2016.7573524\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The measured H-field EMI peak was reduced by around 15dB in a 4-wire single-ended DRAM interface by using a 3-level balanced coding scheme with a 100% pin efficiency. Charge-pump circuits are used to generate 3-level channel signals (-100mV, 0, +100mV) at TX. The RX input comparator uses the ground-level (0) as the voltage reference and employs the meta-stability to identify the ground-level input. The energy efficiency was 2.67pJ/b at 6.4Gb/s with a 65nm LP 1.2V CMOS process and 3-inch FR-4.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"45 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573524\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573524","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme
The measured H-field EMI peak was reduced by around 15dB in a 4-wire single-ended DRAM interface by using a 3-level balanced coding scheme with a 100% pin efficiency. Charge-pump circuits are used to generate 3-level channel signals (-100mV, 0, +100mV) at TX. The RX input comparator uses the ground-level (0) as the voltage reference and employs the meta-stability to identify the ground-level input. The energy efficiency was 2.67pJ/b at 6.4Gb/s with a 65nm LP 1.2V CMOS process and 3-inch FR-4.
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