{"title":"大型退火紧凑型神经网络的构建模块","authors":"M. Laiho, A. Paasio, K. Halonen","doi":"10.1109/ISCAS.2000.856085","DOIUrl":null,"url":null,"abstract":"In this paper the design issues of large globally connected compact neural networks are targeted. Building blocks of a cell that is capable of performing the hardware annealing function are designed. Different offset compensation schemes are used to eliminate the offset currents. The cell is designed to have voltage outputs to facilitate the interconnecting of cells. The blocks are processed with a 0.5 /spl mu/m standard digital CMOS process and measurement results of selected building blocks of the cell are included.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Building blocks for large annealed compact neural networks\",\"authors\":\"M. Laiho, A. Paasio, K. Halonen\",\"doi\":\"10.1109/ISCAS.2000.856085\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper the design issues of large globally connected compact neural networks are targeted. Building blocks of a cell that is capable of performing the hardware annealing function are designed. Different offset compensation schemes are used to eliminate the offset currents. The cell is designed to have voltage outputs to facilitate the interconnecting of cells. The blocks are processed with a 0.5 /spl mu/m standard digital CMOS process and measurement results of selected building blocks of the cell are included.\",\"PeriodicalId\":6422,\"journal\":{\"name\":\"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2000.856085\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2000.856085","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Building blocks for large annealed compact neural networks
In this paper the design issues of large globally connected compact neural networks are targeted. Building blocks of a cell that is capable of performing the hardware annealing function are designed. Different offset compensation schemes are used to eliminate the offset currents. The cell is designed to have voltage outputs to facilitate the interconnecting of cells. The blocks are processed with a 0.5 /spl mu/m standard digital CMOS process and measurement results of selected building blocks of the cell are included.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
