128通道尖峰排序处理器，每通道0.175µW, 0.0033 mm2, 65nm CMOS

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573467

S. Zeinolabedin, A. Do, Dongsuk Jeon, D. Sylvester, T. T. Kim

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引用次数: 20

摘要

本文提出了一种功率和面积有效的实时神经尖峰排序处理器。我们提出了一个鲁棒spike检测器(SD)、一个特征提取器(FE)和一个改进的k-means算法来提高聚类精度。此外，SD采用时复用架构，实现动态功耗降低。还实现了定制的39kb 8T SRAM，以最大限度地减少泄漏和存储面积。该处理器功耗为0.175 μW/ch，在0.54 V时漏损为0.03 μW/ch，面积为0.0033 mm2/ch。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS

This paper presents a power and area efficient processor for real-time neural spike-sorting. We propose a robust spike detector (SD), a feature extractor (FE), and an improved k-means algorithm for better clustering accuracy. Furthermore, time-multiplexing architecture is used in SD for dynamic power reduction. A customized 39kb 8T SRAM is also implemented to minimize leakage and storage area. The proposed processor consumes 0.175 μW/ch with leakage of 0.03 μW/ch at 0.54 V and area of 0.0033 mm2/ch.

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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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