350mV-900mV 2.1GHz 0.011mm2正则表达式匹配加速器，14nm三栅极CMOS耐老化低vmin电路

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573514

A. Agarwal, S. Hsu, M. Anders, S. Mathew, Gregory K. Chen, Himanshu Kaul, Sudhir K. Satpathy, R. Krishnamurthy

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引用次数: 0

摘要

采用14nm三栅极CMOS工艺制作了一种正则表达式匹配片上加速器，该加速器由混合确定性有限自动机(HDFA)和布隆滤波器(BLM)组成，测量工作频率为2.1GHz，占地0.011mm2。HDFA集成了基于概率的截断、唯一转换状态对隔离、并行公共转换检测和NFA空转换。BLM实现了融合的2哈希NOR匹配位线、1位读电路和稀疏H3哈希。这些技术和耐老化的读/写寄存器文件电路(120mV/180mV改进VMIN)实现了350mV- 900mv宽动态电压范围，峰值吞吐量为15.2Gbps-17.1Gbps，在750mV, 25°C下测量3.7mW-4.5mW，在接近阈值的350mV下测量的最大能效为17.5Tbps/W-12.5 tbps /W。

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A 350mV–900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS

A regular expression matching on-die accelerator, consisting of a hybrid deterministic finite automata (HDFA) and Bloom filter (BLM), with measured 2.1GHz operation, is fabricated in 14nm tri-gate CMOS and occupies 0.011mm2. HDFA integrates probability-based truncation, unique transition-state pairs isolation, parallel common transitions detection, and NFA empty transitions. BLM implements a fused 2-hash NOR match bit-line, 1bit read circuits, and sparse H3 hash. These techniques and aging-tolerant read/write register file circuits (120mV/180mV improved VMIN) achieve 350mV-900mV wide dynamic voltage range with peak throughput of 15.2Gbps-17.1Gbps consuming 3.7mW-4.5mW measured at 750mV, 25°C and maximum energy-efficiency of 17.5Tbps/W-12.5Tbps/W measured at near-threshold 350mV.

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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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