{"title":"在低于0.18 /spl mu/m技术下高速缓存设计的数据感知方案的缩放","authors":"K. Zhang, K. Hose, V. De, B. Senyk","doi":"10.1109/VLSIC.2000.852898","DOIUrl":null,"url":null,"abstract":"Small signal differential data sensing for on-chip cache design is evaluated from the perspective of technology scaling. Maintaining the delay scaling trend and high area efficiency is getting more difficult with the conventional scheme as Si process technology moves beyond 0.18 /spl mu/m. An alternative design scheme with large signal sensing is proposed and proven to be a viable design alternative in the deep sub-micron regime.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"39 1","pages":"226-227"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"49","resultStr":"{\"title\":\"The scaling of data sensing schemes for high speed cache design in sub-0.18 /spl mu/m technologies\",\"authors\":\"K. Zhang, K. Hose, V. De, B. Senyk\",\"doi\":\"10.1109/VLSIC.2000.852898\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Small signal differential data sensing for on-chip cache design is evaluated from the perspective of technology scaling. Maintaining the delay scaling trend and high area efficiency is getting more difficult with the conventional scheme as Si process technology moves beyond 0.18 /spl mu/m. An alternative design scheme with large signal sensing is proposed and proven to be a viable design alternative in the deep sub-micron regime.\",\"PeriodicalId\":6361,\"journal\":{\"name\":\"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)\",\"volume\":\"39 1\",\"pages\":\"226-227\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"49\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2000.852898\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2000.852898","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The scaling of data sensing schemes for high speed cache design in sub-0.18 /spl mu/m technologies
Small signal differential data sensing for on-chip cache design is evaluated from the perspective of technology scaling. Maintaining the delay scaling trend and high area efficiency is getting more difficult with the conventional scheme as Si process technology moves beyond 0.18 /spl mu/m. An alternative design scheme with large signal sensing is proposed and proven to be a viable design alternative in the deep sub-micron regime.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
