采用原子开关的2倍逻辑密度可编程逻辑阵列,完全实现40nm及以上节点的逻辑晶体管

Y. Tsuji, X. Bai, A. Morioka, M. Miyamura, R. Nebashi, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, H. Hada, T. Sugibayashi
{"title":"采用原子开关的2倍逻辑密度可编程逻辑阵列,完全实现40nm及以上节点的逻辑晶体管","authors":"Y. Tsuji, X. Bai, A. Morioka, M. Miyamura, R. Nebashi, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, H. Hada, T. Sugibayashi","doi":"10.1109/VLSIC.2016.7573461","DOIUrl":null,"url":null,"abstract":"Programmable Logic (PL) with a high logic density is demonstrated by cross-bar (xbar) of atom switches, which are programmed through logic transistors. The PL has 4 4-input LUTs to minimize area-delay product owing to small area & capacitance of atom switch. Xbar with 50% and 100% populations mixed and programming lines shared architecture achieves a 2× higher logic density comparing to a commercial PL chip on same technology node of 40 nm. 3× higher operation frequency and 40% lower power consumption are also assessed.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"32 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond\",\"authors\":\"Y. Tsuji, X. Bai, A. Morioka, M. Miyamura, R. Nebashi, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, H. Hada, T. Sugibayashi\",\"doi\":\"10.1109/VLSIC.2016.7573461\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Programmable Logic (PL) with a high logic density is demonstrated by cross-bar (xbar) of atom switches, which are programmed through logic transistors. The PL has 4 4-input LUTs to minimize area-delay product owing to small area & capacitance of atom switch. Xbar with 50% and 100% populations mixed and programming lines shared architecture achieves a 2× higher logic density comparing to a commercial PL chip on same technology node of 40 nm. 3× higher operation frequency and 40% lower power consumption are also assessed.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"32 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573461\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573461","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

通过逻辑晶体管对原子开关进行编程,证明了可编程逻辑(PL)具有较高的逻辑密度。由于原子开关的面积小,电容小,因此PL具有4个4输入lut,以最大限度地减少面积延迟产品。Xbar采用50%和100%人口混合和编程线共享架构,与40 nm相同技术节点上的商用PL芯片相比,逻辑密度提高了2倍。工作频率提高3倍,功耗降低40%。
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A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond
Programmable Logic (PL) with a high logic density is demonstrated by cross-bar (xbar) of atom switches, which are programmed through logic transistors. The PL has 4 4-input LUTs to minimize area-delay product owing to small area & capacitance of atom switch. Xbar with 50% and 100% populations mixed and programming lines shared architecture achieves a 2× higher logic density comparing to a commercial PL chip on same technology node of 40 nm. 3× higher operation frequency and 40% lower power consumption are also assessed.
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