电网设计中电迁移寿命评估的冗余方法

2013 IEEE International Interconnect Technology Conference - IITC Pub Date : 2013-06-13 DOI:10.1109/IITC.2013.6615570

B. Ouattara, L. Doyen, D. Ney, H. Mehrez, P. Bazargan-Sabet, F. Bana

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引用次数: 5

摘要

半导体市场在小芯片上增加元件密度的趋势导致了诸如电迁移(EM)等可靠性问题。这种现象在深亚微米设计技术中变得至关重要。在本文中，我们通过考虑冗余路径在电磁退化情况下的贡献来评估芯片电网寿命。将该方法应用于32nm微处理器的导线寿命验证，大大减少了仿真工具给出的易受电磁干扰的导线。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Redundancy method to assess electromigration lifetime in power Grid design

The tendency of semiconductor market to increase component density in small chip leads to reliability issues such as Electromigration (EM). This phenomenon becomes critical in deep submicron design technology. In this paper we assess chip power grid lifetimes by taking into account redundant paths contribution in case of EM degradation. The application of this method for wire lifetime validation of a 32nm microprocessor has reduced significantly wires susceptible to EM given by simulation tools.

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2013 IEEE International Interconnect Technology Conference - IITC

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