Pub Date : 2013-09-30DOI: 10.1109/IITC.2013.6615568
T. Usami, Tomoyuki Nakamura, I. Yashima
We have developed High Load Indentation (HiLI) test as a novel early screening method of Chip-Package Interaction (CPI) for multi-layer Cu/Low-k interconnects structure with bumps. In this study, by using HiLI test, we evaluated a lower fracture toughness SiCOH (Low-k), a thicker under bump metallization (UBM) and a plasma-damaged polyimide (PI) around these bumps, whose white bump failures relatively tend to occur compared to the standard structure. We found that both these in-situ load profiles and observations after the test corresponded with these white bump failures. In addition, we compared between a polished bump structure and an un-polished bump one by the test.
{"title":"Early screening method of chip-package interaction for multi-layer Cu/low-k structure using high load indentation test","authors":"T. Usami, Tomoyuki Nakamura, I. Yashima","doi":"10.1109/IITC.2013.6615568","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615568","url":null,"abstract":"We have developed High Load Indentation (HiLI) test as a novel early screening method of Chip-Package Interaction (CPI) for multi-layer Cu/Low-k interconnects structure with bumps. In this study, by using HiLI test, we evaluated a lower fracture toughness SiCOH (Low-k), a thicker under bump metallization (UBM) and a plasma-damaged polyimide (PI) around these bumps, whose white bump failures relatively tend to occur compared to the standard structure. We found that both these in-situ load profiles and observations after the test corresponded with these white bump failures. In addition, we compared between a polished bump structure and an un-polished bump one by the test.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"43 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77545297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615561
Yue Zhang, Li Zheng, M. Bakir
Embedded microfluidic cooling is considered a promising solution for heat removal in 3D ICs. This paper presents tier-independent microfluidic cooling in a 2-tier chip thermal testbed. Each tier has 4 segmented heaters emulating a simplified multicore processor. Tier-independent cooling is shown to reduce the pumping power by 37.5% by preventing over-cooling when an operating temperature is specified. Thermal coupling for 3D chips with liquid cooling is also discussed.
{"title":"Tier-independent microfluidic cooling for heterogeneous 3D ICs with nonuniform power dissipation","authors":"Yue Zhang, Li Zheng, M. Bakir","doi":"10.1109/IITC.2013.6615561","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615561","url":null,"abstract":"Embedded microfluidic cooling is considered a promising solution for heat removal in 3D ICs. This paper presents tier-independent microfluidic cooling in a 2-tier chip thermal testbed. Each tier has 4 segmented heaters emulating a simplified multicore processor. Tier-independent cooling is shown to reduce the pumping power by 37.5% by preventing over-cooling when an operating temperature is specified. Thermal coupling for 3D chips with liquid cooling is also discussed.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"45 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78141794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615585
L. Hofmann, I. Schubert, K. Gottfried, S. Schulz, T. Gessner
For considerations of stress reduction HAR-TSVs were only partially filled with copper. A comparison was made to ring shaped TSVs (i.e. copper ring with silicon core). Two approaches regarding the way of TSV implementation (before and after wafer bonding/ thinning, resp.) are discussed, concerning process ability and yield aspects. Electrical measurement yield 11 MΩ for a single TSV and 76 MΩ for a 4-point TSV-chain (incl. RDL).
{"title":"Investigations on partially filled HAR tsvs for MEMS applications","authors":"L. Hofmann, I. Schubert, K. Gottfried, S. Schulz, T. Gessner","doi":"10.1109/IITC.2013.6615585","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615585","url":null,"abstract":"For considerations of stress reduction HAR-TSVs were only partially filled with copper. A comparison was made to ring shaped TSVs (i.e. copper ring with silicon core). Two approaches regarding the way of TSV implementation (before and after wafer bonding/ thinning, resp.) are discussed, concerning process ability and yield aspects. Electrical measurement yield 11 MΩ for a single TSV and 76 MΩ for a 4-point TSV-chain (incl. RDL).","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"4 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79542113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615549
N. Nagaraj
Summary form only given. This talk covers the fascinating aspects of the whole spectrum of interconnects from trenches of silicon in nanometers to multi-millimeter long wires at system level and how common principles govern them. This talk starts at the silicon level, where double and triple patterning is becoming more common at lower level interconnects and these offer unique challenges and opportunities in manufacturability, variability and signal/power integrities. Then, it covers the CMP and inter-layer variation induced challenges and opportunities at global interconnects in silicon and expands to interposer and TSV aspects. This is followed by package and board level challenges and opportunities in manufacturability, electromagnetic interference and signal/power integrities. A concept of `Interconnect Continuum' is introduced to show how viewing the whole spectrum in continuity helps in optimizing performance, power, cost and overall reliability.
{"title":"Spanning the spectrum of interconnects from trenches of double patterning to system level","authors":"N. Nagaraj","doi":"10.1109/IITC.2013.6615549","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615549","url":null,"abstract":"Summary form only given. This talk covers the fascinating aspects of the whole spectrum of interconnects from trenches of silicon in nanometers to multi-millimeter long wires at system level and how common principles govern them. This talk starts at the silicon level, where double and triple patterning is becoming more common at lower level interconnects and these offer unique challenges and opportunities in manufacturability, variability and signal/power integrities. Then, it covers the CMP and inter-layer variation induced challenges and opportunities at global interconnects in silicon and expands to interposer and TSV aspects. This is followed by package and board level challenges and opportunities in manufacturability, electromagnetic interference and signal/power integrities. A concept of `Interconnect Continuum' is introduced to show how viewing the whole spectrum in continuity helps in optimizing performance, power, cost and overall reliability.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"8 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78527829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615560
J. Kawahara, I. Kume, H. Honda, Y. Kyogoku, F. Ito, M. Hane, K. Kata, Y. Hayashi
A model-base prediction method is proposed for delamination/cracking failures in Low-k/Cu interconnects with Pb-free FCBGA (Flip Chip-Ball Grid Array). The low-k failure under the solder bump, so called as a white bump (WB) failure, is caused by large thermal stress to a brittle low-k film during the cooling process from high reflow temperature for the Pb-free solder. Based on failure analysis using several low-k films and several packaging materials/structures, we found that occurrence of the WB failure is able to be predicted by a simple evaluation function of the simulated strain energy and a critical energy release rate of crack, which is defined by the fracture toughness and the adhesion-strength of the low-k film. According to this method, we can lead a preliminary design guideline on the bump pitch/structure or the interposer material/structure toward no WE failure quickly.
{"title":"A simple model-base prediction method for delamination failures in Low-k/cu interconnects with flip chip packages","authors":"J. Kawahara, I. Kume, H. Honda, Y. Kyogoku, F. Ito, M. Hane, K. Kata, Y. Hayashi","doi":"10.1109/IITC.2013.6615560","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615560","url":null,"abstract":"A model-base prediction method is proposed for delamination/cracking failures in Low-k/Cu interconnects with Pb-free FCBGA (Flip Chip-Ball Grid Array). The low-k failure under the solder bump, so called as a white bump (WB) failure, is caused by large thermal stress to a brittle low-k film during the cooling process from high reflow temperature for the Pb-free solder. Based on failure analysis using several low-k films and several packaging materials/structures, we found that occurrence of the WB failure is able to be predicted by a simple evaluation function of the simulated strain energy and a critical energy release rate of crack, which is defined by the fracture toughness and the adhesion-strength of the low-k film. According to this method, we can lead a preliminary design guideline on the bump pitch/structure or the interposer material/structure toward no WE failure quickly.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"17 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88023710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615550
Fei Liu, B. Fletcher, E. Joseph, Yu Zhu, J. Gonsalves, W. Price, G. Fritz, S. Engelmann, A. Pyzyna, Zhen Zhang, C. Cabral, M. Guillorn
The resistivity of W interconnects deposited by physical vapor deposition (PVD) and chemical vapor deposition (CVD) is studied. The impacts of the deposition process and liner film stacks are explored. The results show acceptable resistivity for local interconnect (LI) applications with a linewidth down to 20nm and a wiring pitch down to 60nm. An integration scheme for combining a CVD W contact and local interconnect is explored as a means of providing a compact wiring solution with minimal impact on process complexity. The wiring concept is validated by integrating the local interconnects with trigate transistors.
{"title":"Subtractive W contact and local interconnect co-integration (CLIC)","authors":"Fei Liu, B. Fletcher, E. Joseph, Yu Zhu, J. Gonsalves, W. Price, G. Fritz, S. Engelmann, A. Pyzyna, Zhen Zhang, C. Cabral, M. Guillorn","doi":"10.1109/IITC.2013.6615550","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615550","url":null,"abstract":"The resistivity of W interconnects deposited by physical vapor deposition (PVD) and chemical vapor deposition (CVD) is studied. The impacts of the deposition process and liner film stacks are explored. The results show acceptable resistivity for local interconnect (LI) applications with a linewidth down to 20nm and a wiring pitch down to 60nm. An integration scheme for combining a CVD W contact and local interconnect is explored as a means of providing a compact wiring solution with minimal impact on process complexity. The wiring concept is validated by integrating the local interconnects with trigate transistors.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"2014 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86479509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615580
M. Katagiri, H. Miyazaki, Y. Yamazaki, Li Zhang, Takashi Matsumoto, M. Wada, A. Kajita, T. Sakai
We fabricate multilayer graphene interconnects with 100-nm-class line widths. Multilayer graphene is grown on a Ni catalyst layer using remote plasma-enhanced chemical vapor deposition (CVD) at a low temperature of 600°C and transferred onto a SiO2/Si substrate after exfoliation from the Ni layer. The sheet resistance of the CVD graphene interconnects is as low as 500 Ω sq. The temperature dependence of resistance reveals that the CVD graphene exhibits half-metallic transport properties.
{"title":"Electrical properties of multilayer graphene interconnects prepared by chemical vapor deposition","authors":"M. Katagiri, H. Miyazaki, Y. Yamazaki, Li Zhang, Takashi Matsumoto, M. Wada, A. Kajita, T. Sakai","doi":"10.1109/IITC.2013.6615580","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615580","url":null,"abstract":"We fabricate multilayer graphene interconnects with 100-nm-class line widths. Multilayer graphene is grown on a Ni catalyst layer using remote plasma-enhanced chemical vapor deposition (CVD) at a low temperature of 600°C and transferred onto a SiO2/Si substrate after exfoliation from the Ni layer. The sheet resistance of the CVD graphene interconnects is as low as 500 Ω sq. The temperature dependence of resistance reveals that the CVD graphene exhibits half-metallic transport properties.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"4 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88913778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615597
C. Pan, A. Naeemi
This paper provides a fast and efficient approach to analyze and compare systems implemented with through-silicon via (TSV) and monolithic inter-tier via (MIV) 3D integration technologies based on compact models for cycle-per-instruction, memory throughput, and multi-level interconnect networks. Additionally, the impact of via diameter and capacitance on the overall system throughput has been quantified. It is demonstrated that for the same die area and thermal constraint, an MIV-based processor offers over 25% improvement in computational throughput as compared with its 2D counterpart.
{"title":"System-level analysis for 3D interconnection networks","authors":"C. Pan, A. Naeemi","doi":"10.1109/IITC.2013.6615597","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615597","url":null,"abstract":"This paper provides a fast and efficient approach to analyze and compare systems implemented with through-silicon via (TSV) and monolithic inter-tier via (MIV) 3D integration technologies based on compact models for cycle-per-instruction, memory throughput, and multi-level interconnect networks. Additionally, the impact of via diameter and capacitance on the overall system throughput has been quantified. It is demonstrated that for the same die area and thermal constraint, an MIV-based processor offers over 25% improvement in computational throughput as compared with its 2D counterpart.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"21 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84843722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615559
C. S. Liu, H. Pu, C. S. Chen, H. Tsai, C. Lee, M. Lii, Doug C. H. Yu
The key chip-package-integration (CPI) challenges and solutions in the packaging and assembly of advanced Si technology nodes are reported. The key challenge of CPI due to the use of fragile extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) layer has been resolved by optimizing bump structure and materials set including both the organic substrate and solder materials, along with process improvements for both Pb-free solder and Cu bump in flip chip packages.
{"title":"CPI challenges in advanced Si technology nodes","authors":"C. S. Liu, H. Pu, C. S. Chen, H. Tsai, C. Lee, M. Lii, Doug C. H. Yu","doi":"10.1109/IITC.2013.6615559","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615559","url":null,"abstract":"The key chip-package-integration (CPI) challenges and solutions in the packaging and assembly of advanced Si technology nodes are reported. The key challenge of CPI due to the use of fragile extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) layer has been resolved by optimizing bump structure and materials set including both the organic substrate and solder materials, along with process improvements for both Pb-free solder and Cu bump in flip chip packages.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"21 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81607470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615554
Z.-J Wu, L. Cao, J. Im, K.-D. Lee, P. Ho
This paper investigated the initial void growth that determines the electromigration failure time for Cu/low-k interconnects. A method to derive the initial void growth rate prior to line failure by analyzing the resistance traces was developed. The statistical data from multi-linked structures show a linear relationship between the void growth rates before and after failure. An extended the Korhonen model was developed taking into account the stress effect on void growth for Cu interconnects. The model was able to account for the observed EM statistics, thus suggesting that the effect of stress should be included for EM lifetime extrapolation.
{"title":"Critical initial void growth for electromigration: Stress modeling and multi-link statistics for Cu/low-k interconnects","authors":"Z.-J Wu, L. Cao, J. Im, K.-D. Lee, P. Ho","doi":"10.1109/IITC.2013.6615554","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615554","url":null,"abstract":"This paper investigated the initial void growth that determines the electromigration failure time for Cu/low-k interconnects. A method to derive the initial void growth rate prior to line failure by analyzing the resistance traces was developed. The statistical data from multi-linked structures show a linear relationship between the void growth rates before and after failure. An extended the Korhonen model was developed taking into account the stress effect on void growth for Cu interconnects. The model was able to account for the observed EM statistics, thus suggesting that the effect of stress should be included for EM lifetime extrapolation.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"19 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82007846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：